Semiconductor & Computer Engineering
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Difference between revisions of "baikal/baikal-t1"
| Line 23: | Line 23: | ||
| microarch = P5600 | | microarch = P5600 | ||
| platform = | | platform = | ||
| − | | core name = | + | | core name = P5600 |
| core stepping = | | core stepping = | ||
| process = 28 nm | | process = 28 nm | ||
| die size = | | die size = | ||
| − | | word size = 32 | + | | word size = 32 bit |
| core count = 2 | | core count = 2 | ||
| thread count = 2 | | thread count = 2 | ||
| Line 36: | Line 36: | ||
| tdp = 5 W | | tdp = 5 W | ||
| − | | packaging | + | | packaging = Yes |
| − | | package | + | | package 0 = FCBGA-576 |
| − | | package type | + | | package 0 type = FCBGA |
| − | | package pitch | + | | package 0 pins = 576 |
| − | | package | + | | package 0 pitch = |
| − | | socket | + | | package 0 width = 25 mm |
| − | | socket type | + | | package 0 length = 25 mm |
| + | | package 0 height = 1.5 mm | ||
| + | | socket 0 = BGA-576 | ||
| + | | socket 0 type = BGA | ||
}} | }} | ||
| − | The '''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS32]] microprocessor introduced by [[Baikal Electronics]] in 2015. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies]] high-performance P5600 cores | + | The '''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS32]] microprocessor introduced by [[Baikal Electronics]] in 2015. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies]] high-performance P5600 cores and is manufactured on [[TSMC]]'s [[28 nm process]]. |
The chip consumes less than 5W and can be used in fanless designs. | The chip consumes less than 5W and can be used in fanless designs. | ||
== Cache == | == Cache == | ||
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== Memory controller == | == Memory controller == | ||
Revision as of 13:31, 21 March 2017
Template:mpu The Baikal-T1 is a 32-bit dual-core MIPS32 microprocessor introduced by Baikal Electronics in 2015. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of Imagination Technologies high-performance P5600 cores and is manufactured on TSMC's 28 nm process.
The chip consumes less than 5W and can be used in fanless designs.
Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
| Integrated Memory Controller | |
| Type | DDR3-1600 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
Expansions
Networking
The Baikal-T1 has support for 1x10Gb and 2x1Gb Ethernet ports.
| Networking | |
| 1000Base-T | Yes |
| 10GBase-T | Yes |
Block Diagram
