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|introduction=Oct 30, 2012
 
|introduction=Oct 30, 2012
|isa=ARMv8
 
 
|predecessor=Cortex-A15
 
|predecessor=Cortex-A15
 
|predecessor link=arm_holdings/microarchitectures/cortex-a15
 
|predecessor link=arm_holdings/microarchitectures/cortex-a15
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}}
 
}}
 
'''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 
'''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 
== Compiler support ==
 
{| class="wikitable"
 
|-
 
! Compiler !! Arch-Specific || Arch-Favorable
 
|-
 
| [[Arm Compiler]] || <code>-mcpu=cortex-a57</code> || <code>-mtune=cortex-a57</code>
 
|-
 
| [[GCC]] || <code>-mcpu=cortex-a57</code> || <code>-mtune=cortex-a57</code>
 
|-
 
| [[LLVM]] || <code>-mcpu=cortex-a57</code> || <code>-mtune=cortex-a57</code>
 
|}
 
 
If the Cortex-A57 is coupled with the {{\\|Cortex-A53}} in a [[big.LITTLE]] system, GCC also supports the following option:
 
 
{| class="wikitable"
 
|-
 
! Compiler !! Tune
 
|-
 
| [[GCC]] || <code>-mtune=cortex-a57.cortex-a53</code>
 
|}
 
  
 
== Architecture ==
 
== Architecture ==
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== Die ==
 
== Die ==
<table class="wikitable">
+
=== Samsung [[Exynos 5433]] ===
<tr><th colspan="3">Cortex-A57 Clusters Silicon Areas (Estimated)</th></tr>
 
<tr><th>Company</th><td>[[Samsung]]</td><td>[[Renesas]]</td></tr>
 
<tr><th>Chip</th><td>[[Exynos 5433]]</td><td>[[R-Car H3]]</td></tr>
 
<tr><th>Process</th><td>[[20 nm]]</td><td>[[16 nm]]</td></tr>
 
<tr><th>Configuration</th><td>4x Cortex-A57<br>+ 2 MiB L2</td><td>4x Cortex-A57<br>+ 2 MiB L2</td></tr>
 
<tr><th>Cluster Size</th><td>~15.85 mm²</td><td>~10.21 mm² cluster</td></tr>
 
<tr><th>Core Size</th><td>~3 mm²</td><td>~1.66 mm² cluster</td></tr>
 
<tr><th>Cache Size</th><td>~3.87 mm²</td><td>~3.28 mm² cluster</td></tr>
 
</table>
 
 
 
=== 20 nm ===
 
==== Samsung [[Exynos 5433]] ====
 
 
* Samsung [[20 nm process]]
 
* Samsung [[20 nm process]]
 
* 113 mm² die size
 
* 113 mm² die size
 
* Mali-T760 (6 EU)
 
* Mali-T760 (6 EU)
* Quad-core {Primary Cortex-A57 [Quad] + Secondary A53 [Quad]}
+
* Quad-core {{\\|Cortex-A53}} ([[small cores]])
 
** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
 
** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
 
** 4.4 mm² per cluster
 
** 4.4 mm² per cluster
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:[[File:exynos 5433 die.png|600px]]
 
:[[File:exynos 5433 die.png|600px]]
 
=== 16 nm ===
 
==== Renesas [[R-Car H3]] ====
 
* TSMC [[16 nm process]]
 
* 12.94 mm × 8.61 mm
 
* 111.36 mm² die size
 
* Quad-core {{\\|Cortex-A53}}
 
** ~3.27 mm² cluster
 
** ~0.60 mm² core
 
** ~0.7 mm² 512 KiB L2 cache
 
* Quad-core Cortex-A57
 
** ~10.21 mm² cluster
 
** ~1.66 mm² core
 
** ~3.28 mm² 2 MiB L2 cache
 
* {{\\|Cortex-R7}} (dual-core [[lock-step]])
 
** ~1.04 mm² cluster
 
* GX6650 GPU
 
** ~28.12 mm²
 
 
 
: [[File:r-car h3 die shot.png|650px]]
 
 
 
A57 Cluster:
 
 
:[[File:h3 a57 cluster.png|400px]]
 
 
== Bibliography ==
 
* Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
 

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codenameCortex-A57 +
designerARM Holdings +
first launchedOctober 30, 2012 +
full page namearm holdings/microarchitectures/cortex-a57 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A57 +