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| | {{armh title|Ethos}} | | {{armh title|Ethos}} |
| − | {{family
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| − | |name=Ethos
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| − | |image=arm ethos.svg
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| − | |developer=Arm Holdings
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| − | |manufacturer=TSMC
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| − | |manufacturer 2=Samsung
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| − | |manufacturer 3=UMC
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| − | |first announced=October 23, 2019
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| − | |first launched=October 23, 2019
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| − | |microarch=MLP
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| − | }}
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| | '''Ethos''' is a family of [[synthesizable]] [[neural processor]] IPs designed by [[Arm]] for IoT and edge applications. | | '''Ethos''' is a family of [[synthesizable]] [[neural processor]] IPs designed by [[Arm]] for IoT and edge applications. |
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| | == Overview == | | == Overview == |
| − | First introduced in late 2019, Ethos is a family of synthesizable [[neural processor]] IPs designed by Arm for various markets. The Ethos family represents the series of NPUs as part of {{armh|Project Trillium}}. The underlying microarchitecture for all the Ethos NPUs is the {{armh|MLP|l=arch}} which is designed to be scalable through various configurations based on the SRAM sizes and the number of compute engines.
| + | {{empty section}} |
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| | == Members == | | == Members == |
| | === N-Series === | | === N-Series === |
| − | [[File:ethos-n37,57,77 ce config.png|thumb|right|Ethos N37,57,77 CE Configurations.]]
| + | {{empty section}} |
| − | The Ethos-N series was introduced in October 2019. These are fully independent mainstream mobile and IoT NPUs which can be integrated into any SoC just like the {{\\|Cortex}} family. These NPUs come in a preconfigured number of quads and {{armh|MLP#Compute Engine (CE)|compute engines|l=arch}} which can scale from 1-4 [[TOPS]] and from 250 mW up to 1.5 W. Additionally, depending on the exact SKU, the size of the [[SRAM]] bank might be configurable as well. Multiple instances of those IPs may be combined using Arm's {{armh|CCN-500}} or {{armh|CMN-600}} interconnects to scale to higher performance. For example, eight of the {{armh|Ethos-N77|l=core}} can be integrated together on the {{armh|CCN-500}} to scale to 32.8 TOPS (or more using the {{armh|CMN-600}}).
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| − | {| class="wikitable" style="text-align: center;"
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| − | |-
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| − | ! colspan="2" | General || colspan="2" | Configuration || colspan="2" | SRAM || colspan="4" | Compute
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| − | |-
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| − | ! NPU !! Introduction !! Quads !! {{armh|MLP#Compute Engine (CE)|CEs|l=arch}} || Bank || Total || MACs || OPS/clk || [[Int8]] || [[Int16]]
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| − | |-
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| − | | {{armh|Ethos-N37|l=core}} || Oct 23, 2019 || 1 || 4 || 128 KiB || 512 KiB || 512 MACs || 1024 OPs/clk || 1.024 TOPS || 256 GOPS
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| − | | {{armh|Ethos-N57|l=core}} || Oct 23, 2019 || 2 || 8 || 64 KiB || 512 KiB || 1024 MACs || 2048 OPs/clk || 2.048 TOPS || 512 GOPS
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| − | | {{armh|Ethos-N77|l=core}} || Oct 23, 2019 || 4 || 16 || 64 KiB<br>256 KiB || 1 MiB<br>4 MiB || 2048 MACs || 4096 OPs/clk || 4.096 TOPS || 1.024 TOPS
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| − | |}
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| − | | |
| − | === U-Series ===
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| − | The Ethos-U series was introduced in early 2020. This series targets deeply-embedded AI applications. The 'microNPUs' in this series are not complete NPUs like the Ethos-N series. Instead, they feature a much slimmer design. The Ethos-U series is designed to tightly work with a companion Cortex-M processor such as the {{armh|Cortex-M55|l=arch}} (The M55 is preferred due to its {{arm|Helium}} extension support but but other cores such as {{armh|Cortex-M7|M7|l=arch}}, {{armh|Cortex-M4|M4|l=arch}}, and the {{armh|Cortex-M33|M33|l=arch}} should do fine). Conceptually, the U series can be thought of as a single-{{armh|MLP#Compute Engine (CE)|compute engine (CE)|l=arch}} design whereby the {{armh|MLP#Programmable Layer Engine (PLE)|PLE|l=arch}} is removed and instead, relies on using a companion [[Cortex-M]] core for the extra processing. Due to the power and area constraints, the dedicated [[SRAM]] banks are also removed and instead rely on using the shared SoC (or ideally, the Cortex-M cache) for the weights and activations.
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| − | {| class="wikitable" style="text-align: center;"
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| − | |-
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| − | ! colspan="2" | General || colspan="2" | Configuration || colspan="4" | Compute
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| − | |-
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| − | ! NPU !! Introduction !! SRAM || MACs || OPS/clk || Performance (Int8)
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| − | |-
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| − | | {{armh|Ethos-U55|l=core}} || February 10 || Shared with Cortex || 32-256 || 64-512 OPs/clk || 25.6-204.8 [[GOPS]] (@ 100-400 MHz, typical on [[55nm|50]]/[[40nm|40]] nm)<br>64-512 [[GOPS]] (@ 1 GHz, typical on [[16nm|16]]/[[7nm|7]]/[[5nm|5]] nm)
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| − | |}
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| | == See also == | | == See also == |
| | * Intel Habana {{habana|HL|HL Series}} | | * Intel Habana {{habana|HL|HL Series}} |
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