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| − | {{arm title|ARMv1}}{{arm isa main}} | + | {{arm title|ARMv1}} |
| − | '''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{acorn|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{acorn|ARM1}} and was replaced soon after by the {{acorn|ARM2}}. Only a few hundred of those chips were ever fabricated. | + | '''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{armh|ARM1}} and was replaced soon after by the {{armh|ARM2}}. Only a few hundred of those chips were ever fabricated. |
| | | | |
| | == Overview == | | == Overview == |
| − | The ARMv1 presents a simple instruction set architecture, albeit bigger and more complex than many of its [[RISC]] contemporaries, consisting of mostly simple operations along with a number of complex ones borrowed from early {{arch|8}} CISC microprocessors. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit [[program counter]] allowing for a 26-bit address space of up to 64 MiB of memory. | + | The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a [[program counter]] which is 26 bits in size allowing for an address space of up to 64 MiB of data. |
| | | | |
| | == Registers == | | == Registers == |
| − | There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}} and 14, all registers are orthogonal with no specific designated purpose. | + | There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}}, all registers are orthogonal with no specific designated purpose. |
| − | | |
| − | == Addressing Mode ==
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| − | The ARMv1 has five addressing modes:
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| − | | |
| − | {| class="wikitable"
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| − | |-
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| − | ! Mode !! Syntax !! Operation
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| − | |-
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| − | | PC Relative || Label || Effective_Address = PC ± Offset (12 bits)
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| − | |-
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| − | | Base Register Offset<br>With Post-Increment || [Rn], offset || Effective_Address = Rn<br>Rn = Rn ± offset
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| − | |-
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| − | | Base Register Offset<br>With Pre-Increment || [Rn, offset] || Effective_Address = Rn ± offset (12 bits)<br>Rn = Rn ± offset
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| − | |-
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| − | | Base Register Index<br>With Post-Increment || [Rn], Rm || Effective_Address = Rn<br>Rn = Rn ± Rm
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| − | |-
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| − | | Base Register Index<br>With Pre-Increment || [Rn, Rm] || Effective_Address = Rn ± Rm<br>Rn = Rn ± Rm
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| − | |}
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| | | | |
| | == Instruction Listing == | | == Instruction Listing == |
| − | The ARMv1 ISA has 45 operations under 23 mnemonics. The ARMv1 is broken down into 8 classes of instruction:
| + | The ARMv1 is broken down into 2 classes of instruction: |
| | | | |
| − | * [[#movement_instructions|Movement Instructions]]
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| | * [[#load_instructions|Load Instructions]] | | * [[#load_instructions|Load Instructions]] |
| | * [[#store_instructions|Store Instructions]] | | * [[#store_instructions|Store Instructions]] |
| − | * [[#arithmetic_instructions|Arithmetic Instructions]]
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| − | * [[#logical_instructions|Logical Instructions]]
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| − | * [[#comparison_instructions|Comparison Instructions]]
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| − | * [[#branch_instructions|Branch Instructions]]
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| − | * [[#miscellaneous_instructions|Miscellaneous Instructions]]
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| | | | |
| | {{isa | | {{isa |
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| | | listing = | | | listing = |
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| − | {{inst|cols=5|section=<span id="movement_instructions">'''Movement Instructions'''</span><br><small>Movement instructions move data between registers and operands.</small>}} | + | {{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span>}} |
| − | {{inst|mn=MOV |col 1=MOV<cond>{S} Rd, #imm |col 2=Move value immed |col 3 = Rd = immed}} | + | {{inst|mn=LDR |col 1=LDR{cond} Rd, address |col 2=Load [[Word]] |col 3 = Rd = [address]}} |
| − | {{inst|mn=MOV |col 1=MOV<cond>{S} Rd, Rm, {, <shift>} |col 2=Move value |col 3 = Rd = Shift(Rm) }} | + | {{inst|mn=LDRT |col 1=LDRT{cond} Rd, address |col 2=Load [[Word]], User Mode Privilege |col 3 = Rd = [address]}} |
| − | {{inst|mn=MVN |col 1=MVN<cond>{S} Rd, #imm |col 2=Move NOT value immed |col 3 = Rd = {{l|not|immed}}}} | + | {{inst|mn=LDRB |col 1=LDRB{cond} Rd, address |col 2=Load [[Byte]] |col 3 = Rd = ZeroExtend([address])}} |
| − | {{inst|mn=MVN |col 1=MVN<cond>{S} Rd, Rm, {, <shift>} |col 2=Move NOT value |col 3 = Rd = {{l|not|Shift(Rm) }}}} | + | {{inst|mn=LDRBT|col 1=LDRBT{cond} Rd, address |col 2=Load [[Byte]], User Mode Privilege |col 3 = Rd = ZeroExtend([address])}} |
| | + | {{inst|mn=LDM |col 1=LDM{cond}{type} Rn[!], {reglist} |col 2= Load Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> Rd = [addr]<br> addr += {type} }} |
| | + | {{inst|mn=LDM |col 1=LDM{cond}{type} Rn[!], {reglist, PC} |col 2= Load Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> Rd = [addr]<br> addr += {type}<br>R15 = [addr] }} |
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| − | {{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span><br><small>Load instructions move the content of memory addresses into registers.</small>}} | + | {{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span>}} |
| − | {{inst|mn=LDM |col 1=LDM<cond><type> Rn{!}, <reglist>{^} |col 2= Load multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> Rd = [addr]<br> update address based on {type} }} | + | {{inst|mn=STR |col 1=STR{cond} Rd, address |col 2=Store Word |col 3 = [address] = Rd}} |
| − | {{inst|mn=LDR |col 1=LDR<cond>{B} Rd, [Rn {, #imm}]{!} |col 2=Load register immed |col 3 = Rd = [Rn + imm]<br>If !: Rn = Rn + imm}} | + | {{inst|mn=STRT |col 1=STRT{cond} Rd, address |col 2=Store Word, User Mode Privilege |col 3 = [address] = Rd}} |
| − | {{inst|mn=LDR |col 1=LDR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!} |col 2=Load register |col 3 = Rd = [Rn + Shift(Rm)]<br>If !: Rn = Rn + Shift(Rm)]}} | + | {{inst|mn=STRB |col 1=STRB{cond} Rd, address |col 2=Store Byte |col 3 = [address][7:0] = Rd[7:0]}} |
| − | {{inst|mn=LDR |col 1=LDR<cond>{B}{T} Rd, [Rn], #imm |col 2=Load register, post index |col 3 = Rd = [Rn]<br>Rn = Rn + imm}} | + | {{inst|mn=STRBT |col 1=STRBT{cond} Rd, address |col 2=Store Byte, User Mode Privilege |col 3 = [address][7:0] = Rd[7:0]}} |
| − | {{inst|mn=LDR |col 1=LDR<cond>{B}{T} Rd, [Rn], Rm {, <shift>} |col 2=Load register, post index |col 3 = Rd = [Rn]<br>Rn = Rn + Shift(Rm) }} | + | {{inst|mn=STM |col 1=STM{cond}{type} Rn[!], {reglist} |col 2= Store Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> [addr] = Rd<br> addr += {type} }} |
| | + | {{inst|mn=STM |col 1=STM{cond}{type} Rn[!], {reglist}^ |col 2= Store Multiple, User Mode Privilege |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> [addr] |
| | + | = Rd<br> Rn += {type} }} |
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| − | {{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span><br><small>Store instructions moves the values from registers into memory.</small>}}
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| − | {{inst|mn=STM |col 1=STM<cond><type> Rn{!}, <reglist>{^} |col 2= Store multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> [addr] = Rd<br> update address based on {type} }}
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| − | {{inst|mn=STR |col 1=STR<cond>{B} Rd, [Rn {, #imm}]{!} |col 2=Store register immed |col 3 = [Rn + imm] = Rd<br>If !: Rn = Rn + imm}}
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| − | {{inst|mn=STR |col 1=STR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!} |col 2=Store register |col 3 = [Rn + Shift(Rm)] = Rd<br>If !: Rn = Rn + Shift(Rm)]}}
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| − | {{inst|mn=STR |col 1=STR<cond>{B}{T} Rd, [Rn], #imm |col 2=Store register, post index |col 3 = [Rn] = Rd<br>Rn = Rn + imm}}
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| − | {{inst|mn=STR |col 1=STR<cond>{B}{T} Rd, [Rn], Rm {, <shift>} |col 2=Store register, post index |col 3 = [Rn] = Rd<br>Rn = Rn + Shift(Rm) }}
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| − |
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| − | {{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span><br><small>Arithmetic instructions perform basic mathematical operations on two operands.</small>}}
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| − | {{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, #imm |col 2=Add and carry immed |col 3 =Rd = Rn + imm + C}}
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| − | {{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Add and carry |col 3 =Rd = Rn + Shift(Rm) + C}}
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| − | {{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, #imm |col 2=Add immed |col 3 =Rd = Rn + imm}}
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| − | {{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm{, <shift>} |col 2=Add |col 3 =Rd = Rn + Shift(Rm) }}
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| − | {{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, #imm |col 2=Reverse subtract immed |col 3 =Rd = imm - Rn}}
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| − | {{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>} |col 2=Reverse subtract |col 3 =Rd = Shift(Rm) - Rn }}
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| − | {{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, #imm |col 2=Reverse subtract with carry immed |col 3 =Rd = imm - Rn - {{l|not|C}}}}
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| − | {{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>} |col 2=Reverse subtract with carry |col 3 =Rd = Shift(Rm) - Rn - {{l|not|C}}}}
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| − | {{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, #imm |col 2=Subtract with carry immed |col 3 =Rd = Rn - imm - {{l|not|C}}}}
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| − | {{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Subtract with carry |col 3 =Rd = Rn - Shift(Rm) - {{l|not|C}}}}
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| − | {{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, #imm |col 2=Subtract immed |col 3 =Rd = Rn - imm}}
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| − | {{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Subtract |col 3 =Rd = Rn - Shift(Rm) }}
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| − |
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| − | {{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span><br><small>Logical instructions perform logical bitwise operations on operands.</small>}}
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| − | {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm |col 2=AND immed |col 3 =Rd = {{l|land2|Rn|imm}}}}
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| − | {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=AND |col 3 =Rd = {{l|land2|Rn|Shift(Rm) }}}}
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| − | {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm |col 2=Bit clear immed |col 3 =Rd = {{l|land2|Rn|{{l|not|imm}}}}}}
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| − | {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Bit clear |col 3 =Rd = {{l|land2|Rn|{{l|not|Rm}}}}}}
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| − | {{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, #imm |col 2=Exclusive OR immed |col 3 =Rd = {{l|xor|Rn|imm}}}}
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| − | {{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Exclusive OR |col 3 =Rd = {{l|xor|Rn|Shift(Rm) }}}}
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| − | {{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, #imm |col 2=Logical OR immed |col 3 =Rd = {{l|lor2|Rn|imm}}}}
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| − | {{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Logical OR |col 3 =Rd = {{l|lor2|Rn|Shift(Rm) }}}}
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| − |
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| − | {{inst|cols=5|section=<span id="comparison_instructions">'''Comparison Instructions'''</span><br><small>Comparison instructions compare two values and set appropriate status flags.</small>}}
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| − | {{inst|mn=CMN |col 1=CMN<cond> Rn, #imm |col 2=Compare negative immed |col 3 =CPSR flags set on (Rn + imm)}}
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| − | {{inst|mn=CMN |col 1=CMN<cond> Rn, Rm{, <shift>} |col 2=Compare negative |col 3 =CPSR flags set on (Rn + Shift(Rm))}}
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| − | {{inst|mn=CMP |col 1=CMP<cond> Rn, #imm |col 2=Compare immed |col 3 =CPSR flags set on (Rn - imm)}}
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| − | {{inst|mn=CMP |col 1=CMP<cond> Rn, Rm{, <shift>} |col 2=Compare |col 3 =CPSR flags set on (Rn - Shift(Rm))}}
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| − | {{inst|mn=TEQ |col 1=TEQ<cond> Rn, #imm |col 2=Test equality immed |col 3 =CPSR flags set on ({{l|xor|Rn|imm}})}}
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| − | {{inst|mn=TEQ |col 1=TEQ<cond> Rn, Rm{, <shift>} |col 2=Test equality |col 3 =CPSR flags set on ({{l|xor|Rn|Shift(Rm) }})}}
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| − | {{inst|mn=TST |col 1=TST<cond> Rn, #imm |col 2=Test bits immed |col 3 =CPSR flags set on ({{l|land2|Rn|imm}})}}
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| − | {{inst|mn=TST |col 1=TST<cond> Rn, Rm{, <shift>} |col 2=Test bits |col 3 =CPSR flags set on ({{l|land2|Rn|Shift(Rm) }})}}
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| − |
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| − | {{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span><br><small>Branch instructions order instruction processing to start elsewhere conditionally or unconditionally.</small>}}
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| − | {{inst|mn=B |col 1=B<cond> imm |col 2=Branch relative |col 3 =PC = PC + address}}
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| − | {{inst|mn=BL |col 1=BL<cond> imm |col 2=Branch and link relative |col 3 =LR = RET<br>PC = PC + address}}
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| − |
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| − | {{inst|cols=5|section=<span id="miscellaneous_instructions">'''Miscellaneous Instructions'''</span><br><small>Any instruction that doesn't belong anywhere else.</small>}}
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| − | {{inst|mn=SWI |col 1=SWI<cond> imm |col 2=Software interrupt |col 3 =LR = RET<br>Execute SWI vector in supervisor mode}}
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| | }} | | }} |
| − |
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| − | == Multiplication and Floating Point ==
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| − | ARMv1 does not have support for multiplication. Software that requires multiplication will have to resort to a software implementation (e.g., [[Shift-and-Add Multiplication]]). This was considerably slow and was consequently added in later ARM versions. Likewise there was no support for hardware floating point or an ability to do such operations on an external FPU coprocessor.
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| − |
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| − | == Exception Vector Map ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Address !! Function !! Priority
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| − | |-
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| − | | 000 0000 || Reset || 0
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| − | |-
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| − | | 000 0004 || Undefined Instruction Trap || 6
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| − | |-
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| − | | 000 0008 || Software Interrupt || 7
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| − | |-
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| − | | 000 000C || Abort (Prefetch) || 5
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| − | |-
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| − | | 000 0010 || Abort (Data) || 2
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| − | |-
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| − | | 000 0014 || Address Exception || 1
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| − | |-
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| − | | 000 0018 || Normal Interrupt (IRQ) || 4
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| − | |-
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| − | | 000 001C || Fast Interrupt (FIRQ) || 3
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