Generally, exceptions in AArch64 is very similar to {{\\|AArch32}}. There are four exception levels (ELn): EL3 - EL0 with EL0 being the least privileged level (application) and getting progressively more privileged than the one below it. Exceptions always go to the same level or a higher level but they can not take you to a lower level. When taking an exception, the exception link register (ELR) associated with the target exception level is written on exception entry and the interrupt masks are also set. Entering AArch64 from {{\\|AArch32}}, the ELR is always [[zero-extended]]. AArch64 {{\\|banked registers}} are banked by exception level, meaning none of the regular (both GPRs and media) are banked. In AArch64, most of the old mechanism found in {{\\|AArch32}} was not necessary because, at any exception level, it's now possible to simply use the dedicated stack pointer. Additionally, the exception link register (ELR) can be used to determine the origin address. This significantly simplifies exceptions under 64-bit operating mode.

Each exception level except for EL0 has its own [[interrupt vector table|vector table]]. The vector in AArch64 was designed to provide additional information about the exception type (sync, {{\\|IRQ}}, {{\\|FIQ}}, error) and origin (EL and register width, and stack pointer info), eliminating the need to check the {{\\|syndrome register}} which was also significantly enhanced to include a more complete classification of exceptions. It's worth noting that the entry in the table was increased from 4 bytes to 32 instructions long (0x80 bytes), meaning instead of just storing the branch, it's now possible to store the handler directly when it is advantageous to do so.