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== Exceptions == | == Exceptions == | ||
− | Generally, exceptions in | + | Generally, exceptions in AAarch64 is very similar to {{\\|AArach32}}. There are four exception levels (ELn): EL3 - EL0 with EL0 being the least privileged level (application) and getting progressively more privileged than the one below it. Exceptions always go to the same level or a higher level but they can not take you to a lower level. When taking an exception, the exception link register (ELR) associated with the target exception level is written on exception entry and the interrupt masks are also set. Entering AAarch64 from {{\\|AAarch32}}, the ELR is always [[zero-extended]]. AArach64 {{\\|banked registers}} are banked by exception level, meaning none of the regular (both GPRs and media) are banked. In AArach64, most of the old mechanism found in {{\\|AAarch32}} was not necessary because, at any exception level, it's now possible to simply use the dedicated stack pointer. Additionally, the exception link register (ELR) can be used to determine the origin address. This significantly simplifies exceptions under 64-bit operating mode. |
{| class="wikitable" | {| class="wikitable" | ||
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| Exception Link Register<br>([[program counter|PC]]) || || ELR_EL1 || ELR_EL2 || ELR_EL3 | | Exception Link Register<br>([[program counter|PC]]) || || ELR_EL1 || ELR_EL2 || ELR_EL3 | ||
|- | |- | ||
− | | Saved/ | + | | Saved/Currnt Process Status Register<br>({{\\|CPSR}}) || || SPSR_EL1 || SPSR_EL2 || SPSR_EL3 |
|} | |} | ||
− | Each exception level except for EL0 has its own [[interrupt vector table|vector table]]. The vector in | + | Each exception level except for EL0 has its own [[interrupt vector table|vector table]]. The vector in AAarch64 was designed to provide additional information about the exception type (sync, {{\\|IRQ}}, {{\\|FIQ}}, error) and origin (EL and register width, and stack pointer info), eliminating the need to check the {{\\|syndrome register}} which was also significantly enhanced to include a more complete classification of exceptions. It's worth noting that the entry in the table was increased from 4 bytes to 16 instructions long, meaning instead of just storing the branch, it's now possible to store the handler directly when it is advantageous to do so. |
== MMU == | == MMU == | ||
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The supported granule sizes are 4 KiB, 16 KiB, and 64 KiB. This corresponds to the size of the smallest page supported as well as the size of the translation tables in memory. Which of the three supported is up to the implementation. | The supported granule sizes are 4 KiB, 16 KiB, and 64 KiB. This corresponds to the size of the smallest page supported as well as the size of the translation tables in memory. Which of the three supported is up to the implementation. | ||
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== Bibliography == | == Bibliography == | ||
* Richard Grisenthwaite. (October 26, 2011). ''"Technology Preview: The ARM Architecture - a View of the Future "''. | * Richard Grisenthwaite. (October 26, 2011). ''"Technology Preview: The ARM Architecture - a View of the Future "''. | ||
* ARM Architecture Group. "Armv8 instruction set overview." vol. PRD03-GENC-010197 (2011). | * ARM Architecture Group. "Armv8 instruction set overview." vol. PRD03-GENC-010197 (2011). |