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Difference between revisions of "amd/ryzen threadripper/1900x"
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'''Ryzen Threadripper 1900X''' is a {{arch|64}} [[deca-core]] high-performance [[x86]] desktop [[microprocessor]] set to be introduced by [[AMD]] in mid-[[2017]]. The 1900X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1900X operates at a base frequency of 3.6 GHz with a [[TDP]] of 125 W and a {{amd|Precision Boost|Boost}} frequency of 4 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
 
'''Ryzen Threadripper 1900X''' is a {{arch|64}} [[deca-core]] high-performance [[x86]] desktop [[microprocessor]] set to be introduced by [[AMD]] in mid-[[2017]]. The 1900X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1900X operates at a base frequency of 3.6 GHz with a [[TDP]] of 125 W and a {{amd|Precision Boost|Boost}} frequency of 4 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
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{{unknown features}}
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== Cache ==
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{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
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{{cache size
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|l1 cache=960 KiB
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|l1i cache=640 KiB
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|l1i break=10x64 KiB
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|l1i desc=4-way set associative
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|l1d cache=320 KiB
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|l1d break=10x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=5 MiB
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|l2 break=10x512 KiB
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|l2 desc=8-way set associative
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|l2 policy=write-back
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|l3 cache=32 MiB
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|l3 break=4x8 MiB
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|l3 desc=16-way set associative
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}}

Revision as of 02:31, 27 June 2017

Template:mpu Ryzen Threadripper 1900X is a 64-bit deca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1900X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1900X operates at a base frequency of 3.6 GHz with a TDP of 125 W and a Boost frequency of 4 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$960 KiB
983,040 B
0.938 MiB
L1I$640 KiB
655,360 B
0.625 MiB
10x64 KiB4-way set associative 
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back
L2$5 MiB
5,120 KiB
5,242,880 B
0.00488 GiB
  10x512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associative 
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Facts about "Ryzen Threadripper 1900X - AMD"
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l1$ size960 KiB (983,040 B, 0.938 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description4-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description8-way set associative +
l2$ size5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +