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| | |designer=AMD | | |designer=AMD |
| | |manufacturer=TSMC | | |manufacturer=TSMC |
| − | |manufacturer 2=GlobalFoundries
| + | |introduction=2020 |
| − | |introduction=October 8, 2020 | + | |process=7 nm+ |
| − | |process=7nm, 12nm | |
| − | |cores=64
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| − | |cores 2=56
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| − | |cores 3=48
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| − | |cores 4=32
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| − | |cores 5=28
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| − | |cores 6=24
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| − | |cores 7=16
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| − | |cores 8=12
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| − | |cores 9=8
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| − | |cores 10=6
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| − | |type=Superscalar
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| − | |oooe=Yes
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| − | |speculative=Yes
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| − | |renaming=Yes
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| − | |stages=19
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| − | |decode=4-way
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| − | |isa=x86-64
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| − | |extension=MOVBE
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| − | |extension 2=MMX
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| − | |extension 3=SSE
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| − | |extension 4=SSE2
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| − | |extension 5=SSE3
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| − | |extension 6=SSSE3
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| − | |extension 7=SSE4A
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| − | |extension 8=SSE4.1
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| − | |extension 9=SSE4.2
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| − | |extension 10=POPCNT
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| − | |extension 11=AVX
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| − | |extension 12=AVX2
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| − | |extension 13=AES
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| − | |extension 14=PCLMUL
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| − | |extension 15=FSGSBASE
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| − | |extension 16=RDRND
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| − | |extension 17=FMA3
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| − | |extension 18=F16C
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| − | |extension 19=BMI
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| − | |extension 20=BMI2
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| − | |extension 21=RDSEED
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| − | |extension 22=ADCX
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| − | |extension 23=PREFETCHW
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| − | |extension 24=CLFLUSHOPT
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| − | |extension 25=XSAVE
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| − | |extension 26=SHA
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| − | |extension 27=UMIP
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| − | |extension 28=CLZERO
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| − | |extension 29=VAES
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| − | |extension 30=VPCLMUL
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| | |predecessor=Zen 2 | | |predecessor=Zen 2 |
| | |predecessor link=amd/microarchitectures/zen 2 | | |predecessor link=amd/microarchitectures/zen 2 |
| | |successor=Zen 4 | | |successor=Zen 4 |
| | |successor link=amd/microarchitectures/zen 4 | | |successor link=amd/microarchitectures/zen 4 |
| | + | |succession=Yes |
| | }} | | }} |
| − | '''Zen 3''' is a [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|Zen 2}}. It was publicly released on October 8, 2020. Mainstream Desktop processors hit shelves on November 5, 2020. | + | '''Zen 3''' is a planned [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen 2}}. |
| | | | |
| | == History == | | == History == |
| | [[File:amd zen future roadmap.jpg|400px|right]] | | [[File:amd zen future roadmap.jpg|400px|right]] |
| − | Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]]. | + | Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]]. |
| | | | |
| | == Codenames == | | == Codenames == |
| − | [[File:amd zen2-3 roadmap.png|thumb|right|Zen 3 on the roadmap]] | + | [[File:amd zen2-3 roadmap.png|400px|right]] |
| | + | {{future information}} |
| | | | |
| − | '''Product Codenames:'''
| |
| | {| class="wikitable" | | {| class="wikitable" |
| | |- | | |- |
| | ! Core !! C/T !! Target | | ! Core !! C/T !! Target |
| | |- | | |- |
| − | | {{amd|Milan|l=core}} || Up to 64/128 || High-end server [[multiprocessors]] | + | | {{amd|Milan|l=core}} || ?/? || High-end server [[multiprocessors]] |
| − | |-
| |
| − | | {{amd|Chagall|l=core}} || Up to 64/128 || Workstation & enthusiasts market processors
| |
| − | |-
| |
| − | | {{amd|Vermeer|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
| |
| − | |-
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| − | | {{amd|Cezanne|l=core}} || Up to 8/16 || Mainstream APUs with GPUs
| |
| − | |}
| |
| − | | |
| − | '''Architectural Codenames:'''
| |
| − | {| class="wikitable"
| |
| − | |-
| |
| − | ! Arch !! Codename
| |
| − | |-
| |
| − | | Core || Cerebrus
| |
| − | |-
| |
| − | | CCD || Breckenridge
| |
| − | |}
| |
| − | | |
| − | == Products ==
| |
| − | {{future information}}
| |
| − | | |
| − | {| class="wikitable"
| |
| − | |-
| |
| − | ! Processor Series !! Cores/Threads !! Market
| |
| − | |-
| |
| − | | EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]]
| |
| − | |-
| |
| − | | {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing
| |
| − | |-
| |
| − | | Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}" || Up to 64/128 || Workstation processors
| |
| | |- | | |- |
| − | | Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors | + | | {{amd|Vermeer|l=core}} || ?/? || Mainstream to high-end desktops & enthusiasts market processors |
| | |- | | |- |
| − | | Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with integrated GPU | + | | {{amd|Renoir|l=core}} || ?/? || Mainstream desktop & mobile processors with GPU |
| | |} | | |} |
| | | | |
| | == Process technology == | | == Process technology == |
| − | Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]] for the Core Compute Die (CCD), the same process used in Zen 2 Refresh processors, as well as [[GlobalFoundries]] [[14 nm process|12nm process]] for the Input/Output Die (IOD). | + | Zen 3 will be fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]]. |
| − | | |
| − | Note: Only the APU series of microprocessors retains the monolithic design, so they are fabricated solely on [[TSMC]]'s [[7 nm process|7nm+ process]].
| |
| − | | |
| − | == Compiler support ==
| |
| − | {| class="wikitable"
| |
| − | |-
| |
| − | ! Compiler !! Arch-Specific || Arch-Favorable
| |
| − | |-
| |
| − | | [[GCC]] || <code>-march=znver3</code> || <code>-mtune=znver3</code>
| |
| − | |-
| |
| − | | [[LLVM]] || <code>-march=znver3</code> || <code>-mtune=znver3</code>
| |
| − | |}
| |
| − | * '''Note:''' Initial support in GCC 10.3 and LLVM 12.0.
| |
| | | | |
| | == Architecture == | | == Architecture == |
| | + | Nothing is currently known about the architectural improvements that is being done to Zen 2. |
| | | | |
| | === Key changes from {{\\|Zen 2}} === | | === Key changes from {{\\|Zen 2}} === |
| − | * CCD | + | * [[7 nm+ process]] (from [[7 nm]]) |
| − | ** Unified 8-core CCX (from 2x 4-Core CCX per CCD)
| + | |
| − | ** 32 MiB L3$ available equally to all cores in CCD.
| |
| − | *** Increased L3 latency (~46 cycles, up from ~40 cycles)
| |
| − | * Core
| |
| − | ** Higher [[IPC]] (AMD self-reported +19% IPC)
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| − | ** Front-end
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| − | *** Increased branch prediction bandwidth
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| − | *** "zero-bubble" branch prediction
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| − | *** L1 BTB doubled from 512 to 1024 entries
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| − | *** Improved prefetching
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| − | *** Improved µop cache
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| − | ** Back-end
| |
| − | *** Floating point unit:
| |
| − | **** FMA latency reduced by 1 cycle from 5 to 4.
| |
| − | **** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
| |
| − | **** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.
| |
| − | **** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughput.
| |
| − | **** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.
| |
| − | *** Integer unit:
| |
| − | **** Integer physical register file increased from 180 to 192 entries
| |
| − | **** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.
| |
| − | **** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.
| |
| − | **** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.
| |
| − | **** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.
| |
| − | *** Load/store:
| |
| − | **** Load throughput increased from 2 to 3, if not 256b.
| |
| − | **** Store throughput increased from 1 to 2, if not 256b.
| |
| − | **** Store queue increase from 48 to 64 slots.
| |
| − | **** Page table walkers tripled from 2 to 6 for TLB miss handling.
| |
| | {{expand list}} | | {{expand list}} |
| | | | |
| − | === New Instructions === | + | == References == |
| − | Zen 3 introduced the following ISA enhancements:
| |
| − | | |
| − | * {{x86|VAES}} - 256-bit Vector AES instructions
| |
| − | ** <code>VAESDEC</code> - AES Decryption Round
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| − | ** <code>VAESDECLAST</code> - AES Last Decryption Round
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| − | ** <code>VAESENC</code> - AES Encryption Round
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| − | ** <code>VAESENCLAST</code> - AES Last Encryption Round
| |
| − | * <code>{{x86|VPCLMULQDQ}}</code> - 256-bit Vector Carry-Less Multiplication of Quadwords
| |
| − | * {{x86|PCID}} - Process Context Identifiers
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| − | ** <code>{{x86|INVPCID}}</code> - Invalidate TLB entry(s) in a specified PCID
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| − | * {{x86|INVLPGB}} - Broadcast TLB flushing
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| − | ** <code>INVLPGB</code> - Invalidate TLB entry(s) with broadcast to all processors
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| − | ** <code>TLBSYNC</code> - Synchronize TLB invalidations
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| − | * {{x86|PKU}} - Memory Protection Keys for Users
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| − | ** <code>RDPKRU</code> - Read Protection Key Rights
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| − | ** <code>WRPKRU</code> - Write Protection Key Rights
| |
| − | * {{x86|CET|CET_SS}} - Control-flow Enforcement Technology / Shadow Stack
| |
| − | ** <code>CLRSSBSY</code>, <code>INCSSP</code>, <code>RDSSP</code>, <code>RSTORSSP</code>, <code>SAVEPREVSSP</code>, <code>SETSSBSY</code>, <code>WRSS</code>, <code>WRUSS</code>
| |
| − | * {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging
| |
| − | ** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code>
| |
| − | * {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf"/>
| |
| − | | |
| − | Sources: <ref name="amd-24593-apm2"/><ref name="amd-24594-apm3"/><ref name="amd-26568-apm4"/>
| |
| − | | |
| − | === Memory Hierarchy ===
| |
| − | ==== Data and Instruction Caches ====
| |
| − | * L0 Op Cache:
| |
| − | ** 4,096 Ops per core, 8-way set associative
| |
| − | ** 8 Op line size
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| − | ** Parity protected
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| − | * L1I Cache:
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| − | ** 32 KiB per core, 8-way set associative
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| − | ** 64 B line size
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| − | ** Parity protected
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| − | * L1D Cache:
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| − | ** 32 KiB per core, 8-way set associative
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| − | ** 64 B line size
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| − | ** Write-back policy
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| − | ** 4-5 cycles latency for Int
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| − | ** 7-8 cycles latency for FP
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| − | ** ECC
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| − | * L2 Cache:
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| − | ** 512 KiB per core, 8-way set associative
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| − | ** 64 B line size
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| − | ** Write-back policy
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| − | ** Inclusive of L1
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| − | ** ≥ 12 cycles latency
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| − | ** {{abbr|DEC-TED}} ECC, tag & state arrays {{abbr|SEC-DED}}<!--7 check bits for 42 tag bits; AMD-55898-0.50 Sec 3.5-->
| |
| − | * L3 Cache:
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| − | ** "{{amd|Milan|l=core}}" & "{{amd|Chagall|l=core}}": 32 MiB/CCX, up to 256 MiB total
| |
| − | ** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total
| |
| − | ** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs
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| − | ** Shared by all cores in the {{abbr|CCX}}, configurable<ref name="amd-56375-qos"/>
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| − | ** 16-way set associative
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| − | ** 64 B line size
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| − | ** L2 [[victim cache]]
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| − | ** Write-back policy
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| − | ** 46 cycles average load-to-use latency
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| − | ** DEC-TED ECC, tag array & shadow tags SEC-DED<!--AMD-55898-0.50 Sec 3.5-->
| |
| − | ** QoS Monitoring and Enforcement V2.0
| |
| − | | |
| − | ==== Translation Lookaside Buffers ====
| |
| − | * ITLB
| |
| − | ** 64 entry L1 TLB, fully associative, all page sizes
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| − | ** 512 entry L2 TLB, 8-way set associative
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| − | *** 4-Kbyte and 2-Mbyte pages
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| − | ** Parity protected
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| − | * DTLB
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| − | ** 64 entry L1 TLB, fully associative, all page sizes
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| − | ** 2,048 entry L2 TLB, 16-way set associative
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| − | *** 4-Kbyte and 2-Mbyte pages, PDEs to speed up table walks
| |
| − | ** Parity protected
| |
| − | | |
| − | All caches and TLBs are competitively shared in multi-threaded mode.
| |
| − | | |
| − | ==== System DRAM ====
| |
| − | * EPYC 7003 "{{amd|Milan|l=core}}":
| |
| − | ** 8 channels per socket, up to 16 DIMMs, max. 4 TiB
| |
| − | ** Up to PC4-25600L (DDR4-3200)
| |
| − | ** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}, {{abbr|NVDIMM-N}}
| |
| − | ** ECC supported (x4, x8, x16, chipkill)<!--AMD-55898-0.50 Sec 3.7-->
| |
| − | ** DRAM bus parity and write data CRC options<!--ibid-->
| |
| − | | |
| − | * Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}":
| |
| − | ** 8 channels, up to 8 DIMMs, max. 2 TiB
| |
| − | ** Up to PC4-25600L (DDR4-3200)
| |
| − | ** SR/DR {{abbr|UDIMM}}, RDIMM, LRDIMM, 3DS DIMM
| |
| − | ** ECC supported
| |
| − | | |
| − | * Ryzen 5000 "{{amd|Vermeer|l=core}}":
| |
| − | ** 2 channels, up to 4 DIMMs, max. 128 GiB
| |
| − | ** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported
| |
| − | | |
| − | * Ryzen 5000 APU "{{amd|Cezanne|l=core}}":
| |
| − | ** {{amd|Socket AM4|l=pack}}:
| |
| − | *** 2 channels, up to 4 DIMMs, max. 128 GiB
| |
| − | *** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported ("PRO" models)
| |
| − | ** {{amd|FP6|FP6 package|l=pack}}, DDR4 mode:
| |
| − | *** 2 × 64-bit channels, up to 2 DIMMs, max. 64 GiB
| |
| − | *** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported(?)
| |
| − | ** FP6 package, LPDDR4 mode:
| |
| − | *** 4 × 32-bit channels, max. 32 GiB
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| − | *** Up to LPDDR4X-4266
| |
| − | | |
| − | Sources: <ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h"/><ref name="amd-55898-ppr-1901-0.35"/><ref name="amd-55898-ppr-1901-0.50"/><ref name="amd-56178-mdg-fp6"/>
| |
| − | | |
| − | == All Zen 3 Chips ==
| |
| − | | |
| − | <!-- NOTE:
| |
| − | This table is generated automatically from the data in the actual articles.
| |
| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
| |
| − | created and tagged accordingly.
| |
| − | | |
| − | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
| |
| − | -->
| |
| − | {{comp table start}}
| |
| − | <table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19">
| |
| − | {{comp table header|main|20:List of all Zen 3-based Processors}}
| |
| − | {{comp table header|main|12:Processor|4:Features}}
| |
| − | {{comp table header|cols|Price|Process|Launched|Family|Core|C|T|TDP|L3|Base|Turbo|Max Mem|SMT|SEV|SME|TSME}}
| |
| − | {{comp table header|lsep|25:[[Uniprocessors]]}}
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| − | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::1]]
| |
| − | |?full page name
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| − | |?model number
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| − | |?release price
| |
| − | |?process
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| − | |?first launched
| |
| − | |?microprocessor family
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| − | |?core name
| |
| − | |?core count
| |
| − | |?thread count
| |
| − | |?tdp
| |
| − | |?l3$ size
| |
| − | |?base frequency#GHz
| |
| − | |?turbo frequency#GHz
| |
| − | |?max memory#GiB
| |
| − | |?has simultaneous multithreading
| |
| − | |?has amd secure encrypted virtualization technology
| |
| − | |?has amd secure memory encryption technology
| |
| − | |?has amd transparent secure memory encryption technology
| |
| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |userparam=18:15
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| − | |mainlabel=-
| |
| − | |valuesep=,
| |
| − | |limit=100
| |
| − | }}
| |
| − | {{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}
| |
| − | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::>>1]]
| |
| − | |?full page name
| |
| − | |?model number
| |
| − | |?release price
| |
| − | |?process
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| − | |?first launched
| |
| − | |?microprocessor family
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?tdp
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| − | |?l3$ size
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| − | |?base frequency#GHz
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| − | |?turbo frequency#GHz
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| − | |?max memory#GiB
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| − | |?has simultaneous multithreading
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| − | |?has amd secure encrypted virtualization technology
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| − | |?has amd secure memory encryption technology
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| − | |?has amd transparent secure memory encryption technology
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| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |userparam=18:15
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| − | |mainlabel=-
| |
| − | |valuesep=,
| |
| − | |limit=100
| |
| − | }}
| |
| − | {{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]]}}
| |
| − | </table>
| |
| − | {{comp table end}}
| |
| − | | |
| − | == Designers ==
| |
| − | * Mark Evers, Chief Architect
| |
| − | | |
| − | == Bibliography ==
| |
| | * AMD 'Tech Day', February 22, 2017 | | * AMD 'Tech Day', February 22, 2017 |
| | * AMD 2017 Financial Analyst Day, May 16, 2017 | | * AMD 2017 Financial Analyst Day, May 16, 2017 |
| − |
| |
| − | == References ==
| |
| − | <references>
| |
| − | <ref name="amd-psf">{{cite techdoc|title=White Paper: Security Analysis of AMD Predictive Store Forwarding|url=https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf|publ=AMD|date=2021-03}}</ref>
| |
| − | <ref name="amd-24593-apm2">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 2: System Programming|url=https://www.amd.com/system/files/TechDocs/24593.pdf|publ=AMD|pid=24593|rev=3.37|date=2021-03}}</ref>
| |
| − | <ref name="amd-24594-apm3">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions|url=https://www.amd.com/system/files/TechDocs/24594.pdf|publ=AMD|pid=24594|rev=3.32|date=2021-03}}</ref>
| |
| − | <ref name="amd-26568-apm4">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit and 256-Bit Media Instructions|url=https://www.amd.com/system/files/TechDocs/26568.pdf|publ=AMD|pid=26568|rev=3.24|date=2020-05}}</ref>
| |
| − | <ref name="amd-56375-qos">{{cite techdoc|title=AMD64 Technology Platform Quality of Service Extensions|url=https://developer.amd.com/wp-content/resources/56375.pdf|publ=AMD|pid=56375|rev=1.02|date=2020-10}}</ref>
| |
| − | <ref name="amd-56665-sog-19h">{{cite techdoc|title=Software Optimization Guide for AMD Family 19h Processors (PUB)|url=https://www.amd.com/system/files/TechDocs/56665.zip|publ=AMD|pid=56665|rev=3.00|date=2020-11}}</ref>
| |
| − | <ref name="amd-55898-ppr-1901-0.35">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref>
| |
| − | <ref name="amd-55898-ppr-1901-0.50">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|publ=AMD|pid=55898|rev=0.50|date=2021-05-27}}</ref>
| |
| − | <ref name="amd-56178-mdg-fp6">{{cite techdoc|title=FP6 Processor Motherboard Design Guide|publ=AMD|pid=56178|rev=1.03|date=2020-01}}</ref>
| |
| − | </references>
| |
| | | | |
| | == See Also == | | == See Also == |
| − | * AMD {{\\|Zen}}, {{\\|Zen 2}}, {{\\|Zen 4}} | + | * AMD {{\\|Zen}} |
| | * Intel {{intel|Tigerlake|l=arch}} | | * Intel {{intel|Tigerlake|l=arch}} |
| − | * Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]
| |
| − | * Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews]
| |
