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[[File:amd zen future roadmap.jpg|400px|right]] | [[File:amd zen future roadmap.jpg|400px|right]] | ||
Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]]. | Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]]. | ||
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== Products == | == Products == | ||
+ | [[File:amd zen2-3 roadmap.png|400px|right]] | ||
{{future information}} | {{future information}} | ||
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Note: Only the APU series of microprocessors retains the monolithic design, so they are fabricated solely on [[TSMC]]'s [[7 nm process|7nm+ process]]. | Note: Only the APU series of microprocessors retains the monolithic design, so they are fabricated solely on [[TSMC]]'s [[7 nm process|7nm+ process]]. | ||
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== Architecture == | == Architecture == | ||
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** Higher [[IPC]] (AMD self-reported +19% IPC) | ** Higher [[IPC]] (AMD self-reported +19% IPC) | ||
** Front-end | ** Front-end | ||
− | + | ** Increased branch prediction bandwidth | |
*** "zero-bubble" branch prediction | *** "zero-bubble" branch prediction | ||
*** L1 BTB doubled from 512 to 1024 entries | *** L1 BTB doubled from 512 to 1024 entries | ||
− | + | ** Improved prefetching | |
− | + | ** Improved µop cache | |
− | + | * Back-end | |
− | + | ** Floating point unit: | |
− | + | *** FMA latency reduced by 1 cycle from 5 to 4. | |
− | + | *** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port. | |
− | + | *** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set. | |
− | + | *** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughput. | |
− | + | *** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation. | |
− | + | ** Integer unit: | |
− | + | *** Integer physical register file increased from 180 to 192 entries | |
− | + | *** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways. | |
− | + | *** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each. | |
− | + | *** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams. | |
− | + | *** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately. | |
− | + | ** Load/store: | |
− | + | *** Load throughput increased from 2 to 3, if not 256b. | |
− | + | *** Store throughput increased from 1 to 2, if not 256b. | |
− | + | *** Store queue increase from 48 to 64 slots. | |
− | + | *** Page table walkers tripled from 2 to 6 for TLB miss handling. | |
{{expand list}} | {{expand list}} | ||
Facts about "Zen 3 - Microarchitectures - AMD"
codename | Zen 3 + |
core count | 64 +, 56 +, 48 +, 32 +, 28 +, 24 +, 16 +, 12 +, 8 + and 6 + |
designer | AMD + |
first launched | October 8, 2020 + |
full page name | amd/microarchitectures/zen 3 + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen 3 + |
pipeline stages | 19 + |