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Latest revision | Your text | ||
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**** 2x wider EUs (256-bit FMAs, up from 128-bit FMAs) | **** 2x wider EUs (256-bit FMAs, up from 128-bit FMAs) | ||
**** 2x wider LSU (2x256-bit L/S, up from 128-bit) | **** 2x wider LSU (2x256-bit L/S, up from 128-bit) | ||
− | **** Improved | + | **** Improved mul latency (3 cycles, down from 4) |
*** Integer | *** Integer | ||
**** Increased number of registers (180, up from 168) | **** Increased number of registers (180, up from 168) |
Facts about "Zen 2 - Microarchitectures - AMD"
codename | Zen 2 + |
core count | 4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 64 + |
designer | AMD + |
first launched | July 2019 + |
full page name | amd/microarchitectures/zen 2 + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen 2 + |
pipeline stages | 19 + |