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Difference between revisions of "amd/k5/amd-k5-pr100abq"
< amd‎ | k5

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== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}}
 
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}}
 
 
{{cache info
 
{{cache info
|l1i cache=16 KB
+
|l1i cache=16 KiB
|l1i break=1x16 KB
+
|l1i break=1x16 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=8 KB
+
|l1d cache=8 KiB
|l1d break=1x8 KB
+
|l1d break=1x8 KiB
 
|l1d desc=4-way set associative
 
|l1d desc=4-way set associative
 
|l1d extra=
 
|l1d extra=

Revision as of 00:14, 21 September 2016

Template:mpu AMD-K5-PR100ABQ was a 32-bit x86 microprocessor developed by AMD and released in 1996. This chip was sold as Pentium 100 MHz equivalent. The processor used AMD's 2nd revision of their K5 microarchitecture, operating at 100 MHz with a TDP of 15.8 W.

Cache

Main article: K5 § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1x16 KiB 4-way set associative
L1D$ 8 KiB
0.00781 MiB
8,192 B
7.629395e-6 GiB
1x8 KiB 4-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

  • P100 P-Rating
  • Auto-power down state
  • Stop clock state

Gallery

See also

Facts about "AMD-K5-PR100ABQ - AMD"
l1d$ description4-way set associative +
l1d$ size0.00781 MiB (8 KiB, 8,192 B, 7.629395e-6 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
processor p-ratingP100 +