Editing amd/cores/milan

{{amd title|Milan|core}}
{{core
|name=Milan
|no image=No
|developer=AMD
|manufacturer=TSMC
|first announced=May 16, 2017
|isa=x86-64
|microarch=Zen 3
|word=64 bit
|proc=7 nm
|tech=CMOS
|predecessor=Rome
|predecessor link=amd/cores/rome
|successor=Genoa
|successor link=amd/cores/genoa
|succession=Yes
}}
'''Milan''' is the codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 3|l=arch}} microarchitecture serving as a successor to {{\\|Rome}}. Milan-based chips are set to be fabricated on GlobalFoundries' [[7 nm process]].
@@ Line 2: / Line 2: @@
 {{core
 |name=Milan
-|no image=Yes
+|no image=No
 |developer=AMD
 |manufacturer=TSMC
-|manufacturer 2=GlobalFoundries
+|first announced=May 16, 2017
-|first announced=January 12, 2021
-|first launched=March 15, 2021
 |isa=x86-64
 |microarch=Zen 3
 |word=64 bit
-|proc=7 nm+
+|proc=7 nm
-|proc 2=
 |tech=CMOS
-|package name 1=amd,socket_sp3
 |predecessor=Rome
 |predecessor link=amd/cores/rome
@@ Line 21: / Line 17: @@
 |succession=Yes
 }}
-'''Milan''' is the codename of [[AMD]]'s {{amd|EPYC#7003 Series (Zen 3)|EPYC 7003 series}} of high-performance microprocessors based on the {{amd|Zen 3|l=arch}} microarchitecture for single- and dual-socket server platforms. Launched in March 2021 it succeeded the second generation of EPYC processors, the {{amd|EPYC#7002 Series (Zen 2)|EPYC 7002}} "{{\\|Rome}}" series.<ref name="pr20210315">[https://ir.amd.com/news-events/press-releases/detail/993/amd-epyc-7003-series-cpus-set-new-standard-as-highest "AMD EPYC™ 7003 Series CPUs Set New Standard as Highest Performance Server Processor"] (Press release). AMD.com. March 15, 2021. Retrieved April 2021.</ref>
+'''Milan''' is the codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 3|l=arch}} microarchitecture serving as a successor to {{\\|Rome}}. Milan-based chips are set to be fabricated on GlobalFoundries' [[7 nm process]].
-The codename "Milan" first appeared on AMD roadmaps in 2017. In 2019 a presentation leaked on YouTube and later removed revealed the basic CCD configuration.<ref>Hilgeman, Martin. "Innovator Insights: AMD Epyc for High Performance Computing Workloads". [http://www.hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php HPC-AI conference 2019], September 16, 2019.</ref> The launch of the EPYC 7003 series was announced and a 32-core model demonstrated in a keynote by AMD CEO Lisa Su on January 12, 2021 for [[wikipedia:Consumer Electronics Show|CES]] 2021.
-EPYC 7003 processors identify as members of {{amd|CPUID#Family 25 (19h)|AMD CPU Family 19h, Model 01h}} (engineering samples as Model 00h).
-== Overview ==
-"Milan" development focused on microarchitectural improvements, see the {{amd|Zen 3|l=arch}} article for details. The "Milan" <abbr title="System on a Chip">SoC</abbr>s support single and 2-way multiprocessing as well as 2-way multithreading with up to 64 cores and 128 threads per processor. AMD claims up to 15% better performance per cost and 25% more performance in the mid-stack segment compared to the prior generation.
-The processors are available in a 4094-contact [[land grid array]] package for {{amd|Socket SP3|l=package}} and backwards compatible with motherboards designed for "Rome" processors (EPYC "Type-1" boards) after a BIOS update. Due to limited [[wikipedia:Non-volatile memory|NVM]] capacity this update may remove support for first generation {{amd|EPYC#7001 Series (Zen)|EPYC 7001}} "{{\\|Naples}}" series CPUs. "Type-0" boards designed for the lower memory and PCIe bus frequencies of "Naples" processors are not supported.<ref name="mln-001">[https://www.amd.com/en/claims/epyc#faq-MLN-001 "AMD EPYC™ Family of Processors Claim Information"]. AMD.com. Retrieved May 2021.</ref> The codename of AMD's Type-1 reference platform is "Ethanol X".
-Like the "Rome" series, "Milan" processors are multi-chip modules containing one large I/O die and (as of May 2021) four or eight Core Complex Dies fabricated on a [[TSMC]] advanced [[7 nm process]]. <!-- Singh2020 (doi:10.1109/ISSCC19947.2020.9063113) confirms that Zen 2 is manufactured on a 7 nm process with 6-track cell library (TSMC N7 & H240 HD). Advanced process may refer to TSMC N7P or N7+. Some AMD marketing materials use "7nm+" but this cannot be construed as N7+, see e.g. https://www.anandtech.com/show/15589/amd-clarifies-comments-on-7nm-7nm-for-future-products-euv-not-specified --> The "Rome" CCD integrates two {{amd|Zen 2|l=arch}} Core Complexes (CCX), each providing four CPU cores and a shared 16 MiB L3 cache with 39 cycles average load-to-use latency. In contrast the "Milan" CCD contains a single {{amd|Zen 3|l=arch}} CCX comprising eight CPU cores (the number of usable cores varies by <abbr title="Store Keeping Unit">SKU</abbr>) which share a 32 MiB L3 cache with 46 cycles average latency, doubling the L3 capacity available to one core.
-The "Milan" I/O die has largely the same features as the prior generation die fabricated on [[GlobalFoundries]]' [[14_nm_lithography_process|14 nanometer "14LPP" process]]. <!-- AMD did not disclose manufacturing details about the "Milan" sIOD. A diagram in Publ. #57091 "HPC Tuning for EPYC 7003" labels the die as "14nm". --> Apart of the memory controllers and I/O facilites described below it integrates an {{amd|secure processor|AMD Secure Processor}}, a <abbr title="System Management Unit">SMU</abbr>, <abbr title="Real Time Clock">RTC</abbr>, and other functions traditionally found in a separate chipset.
-In an interview on March 15, 2021 AMD SVP Forrest Norrod confirmed plans for another server processor series based on the Zen 3 microarchitecture with the codename "Trento". These processors will use a different I/O die with additional coherent {{amd|Infinity Fabric}} links to attach accelerators. They will be used in the exaflop [[wikipedia:Frontier_%28supercomputer%29|Frontier]] supercomputer with nodes comprising one EPYC CPU and four Radeon Instinct MI200 GPUs.<ref>"[https://www.anandtech.com/show/16548/interview-with-amd-forrest-norrod-milan The Tour of Italy with EPYC Milan: Interview with AMD's Forrest Norrod]. anandtech.com. Retrieved May 2021.</ref> "Milan" processors will power the 100 petaflop [[wikipedia:Perlmutter_%28supercomputer%29|Perlmutter]] supercomputer, [https://news.iu.edu/stories/2020/06/iub/releases/01-jetstream-cloud-computing-awarded-nsf-grant.html Jetstream 2], [https://www.rcac.purdue.edu/compute/anvil/ Anvil], and a yet-to-be-named HPE Cray EX system at NSCC Singapore.
-=== Memory Interface ===
-The "Milan" I/O die integrates eight [[wikipedia:DDR4 SDRAM|DDR4]] memory controllers (<abbr title="Unified Memory Controller">UMC</abbr>s), two per I/O die quadrant, which achieve data rates from 1333 to 3200 MT/s.<ref name="amd-55898">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref> Up to 2 DIMMs per channel are supported. The {{amd|Infinity Fabric}} and memory bus clock can be coupled to slightly reduce the memory latency, "Milan" processors permit this up to 1600 MHz matching DDR4-3200 memory.<ref name="amd-57091">{{cite techdoc|title=High Performance Computing (HPC) Tuning Guide for AMD EPYC™ 7003 Series Processors|url=https://www.amd.com/system/files/documents/high-performance-computing-tuning-guide-amd-epyc7003-series-processors.pdf|publ=AMD|pid=57091|rev=2.0|date=2021-03}}</ref> The memory controllers support [[wikipedia:ECC memory|ECC memory]] and the following DIMM types:<ref name="amd-56873">{{cite techdoc|title=Memory Population Guidelines for AMD EPYC™ 7003 Series Processors|publ=AMD|pid=56873|rev=0.70|date=2020-11}}</ref>
-* <abbr title="Single Rank">SR</abbr>/<abbr title="Dual Rank">DR</abbr> [[wikipedia:Registered memory|RDIMM]] built with x4 and x8 DDR4 devices
-* <abbr title="Quad Rank">4R</abbr>/<abbr title="Eight Rank">8R</abbr> [[wikipedia:Registered memory|LRDIMM]] built with x4 devices (<abbr title="Quad Rank, two dies">4DR</abbr>, <abbr title="Quad Rank = Dual Rank × 2 dies stacked">2S2R</abbr>, <abbr title="Eight Rank = Dual Rank × 4 dies stacked">2S4R</abbr>)
-* 4R/8R [[3DS DIMM]] built with x4 devices (2S2R, 2S4R)
-* [[wikipedia:NVDIMM|NVDIMM-N]] (DRAM with NVM backup)
-The maximum total memory capacity is 4 TiB per socket using 16 LRDIMMs or 3DS DIMMs of 256 GiB capacity.
-{| class="wikitable" style="display: inline-table; text-align: center;"
-! colspan="4" | Memory speed based on DIMM population
-|-
-! rowspan="2" | DIMM Type || colspan="2" | DIMM Population/Channel || rowspan="2" | Max. Data Rate<br/>(MT/s)
-|-
-! DIMM0 || DIMM1
-|-
-| rowspan="5" | RDIMM || - || 1R || 3200
-|-
-| - || 2R or 2DR || 3200
-|-
-| 1R || 1R || 2933
-|-
-| 1R || 2R or 2DR || 2933
-|-
-| 2R or 2DR || 2R or 2DR || 2933
-|-
-| rowspan="6" | LRDIMM || – || 4DR || 3200
-|-
-| – || 2S2R (4 ranks) || 3200
-|-
-| – || 2S4R (8 ranks) || 3200
-|-
-| 4DR || 4DR || 2933
-|-
-| 2S2R (4 ranks) || 2S2R (4 ranks) || 2933
-|-
-| 2S4R (8 ranks) || 2S4R (8 ranks) || 2933
-|-
-| rowspan="4" | 3DS || – || 2S2R (4 ranks) || 2933
-|-
-| – || 2S4R (8 ranks) || 2933
-|-
-| 2S2R (4 ranks) || 2S2R (4 ranks) || 2666
-|-
-| 2S4R (8 ranks) || 2S4R (8 ranks) || 2666
-|}
-DIMM0 is the module closer to the CPU. This socket is not present on motherboards which support only one DIMM per channel.
-The memory channels are designated A to H. "Rome" and "Milan" processors support 2-, 4-, 8-, and 16-way (on 2P systems) memory interleaving. 4-way mode interleaves the memory channels ABCD and/or EFGH, or CDGH if only these four channels are populated. In contrast to the prior generation CDGH interleaving is supported by all EPYC 7003 <abbr title="Stock Keeping Unit">SKU</abbr>s with 128 MiB L3 cache or less, none having only two <abbr title="Core Complex Die">CCD</abbr>s. Additionally all "Milan" processors support 6-way interleaving if channels B and F remain unpopulated, with a maximum of 256 GiB capacity per channel and restricted to 2 or 4 KiB interleaving size.<ref name="amd-56873"/> The new options enable balanced memory utilization at reduced memory cost when peak memory performance is not required.
-With all UMCs implemented in a central I/O die "Rome" and "Milan" processors have a single [[wikipedia:Non-uniform memory access|NUMA]] domain per socket and two NUMA distances on dual-socket platforms. AMD advertised a flatter NUMA domain and reduced inter-core latency since the <abbr title="Core Complex">CCX</abbr>s were pairwise united and the CPU cores in a CCX can exchange data through the shared L3 cache rather than the {{amd|Infinity Fabric|Scalable Data Fabric}} on the I/O die. "Milan" still supports the ''NUMA Nodes Per Socket'' (NPS) and ''<abbr title="Last Level Cache">LLC</abbr>/L3/CCX as NUMA domain'' BIOS setup options. 6-way memory interleaving is only possible with NPS=1.<ref name="amd-56873"/>
-Finally an unspecified [[probe filter]] improvement was advertised.
-=== Input/Output Interfaces ===
-The "Milan" I/O die integrates eight 16-lane [[wikipedia:PCI Express|PCIe]] Gen 4 (16 GT/s) controllers. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links. Each controller supports up to eight PCIe links. On dual-socket systems four, or optionally three, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these <abbr title="External Global Memory Interconnect, 2nd generation">xGMI-2</abbr> links can reach 18 GT/s. The I/O die also integrates four [[wikipedia:Serial ATA|SATA]] 3.0 (6 Gb/s) controllers which support up to eight links each, multiplexed with the lower eight lanes of four x16 links. [[wikipedia:NVM Express|NVMe]] devices are supported as well. An additional 2-lane PCIe Gen 2 controller powers the WAFL links. One or both of these lanes serve as {{amd|Infinity Fabric#Scalable Control Fabric (SCF)|SCF}} links between sockets and are otherwise available for I/O, e.g. to attach a [[wikipedia:Intelligent Platform Management Interface#Baseboard management controller|BMC]]. In sum up to 128 + 2 PCIe lanes are available per socket and up to 2 × 80 + 2 × 1 = 162 lanes total on dual-socket platforms.<ref name="amd-55898"/>
-With the "Milan" series the integrated <abbr title="Input/Output Memory Management Unit">IOMMU</abbr>s were optimized to better handle high-bandwidth devices such as 200 Gbps Ethernet adapters. Support for hotplug surprise removal was brought up to current [[wikipedia:PCI-SIG|PCI-SIG]] implementation guidelines.
-Four USB 1.1/2.0/3.1 (10 Gb/s) ports are available on the CPU package, and several low-speed interfaces listed below.
-=== Feature Summary ===
-All "Milan" processors have the following features:
-* 8 to 64 {{amd|Zen 3|l=arch}} [[x86]] CPU cores with 2-way [[SMT]]
-** 4,096-entry Op cache, 2 × 32 KiB L1, and 512 KiB L2 cache per core
-** x86 extensions ('''new'''):     {{x86|ABM}}, {{x86|ADX}}, {{x86|AES}}, {{x86|AVX}}, {{x86|AVX2}},  {{x86|BMI1}}, {{x86|BMI2}},   {{x86|CLFLUSH}}, {{x86|CLFLUSHOPT}}, {{x86|CLWB}}, {{x86|CLZERO}}, {{x86|CMOV}}, {{x86|CMPXCHG8B}}, {{x86|CMPXCHG16B}},  {{x86|EMMX}}, {{x86|F16C}},  {{x86|FMA3}},  {{x86|FPU}}, {{x86|FSGSBASE}}, {{x86|FXSR}}, '''{{x86|INVLPGB}}''', '''{{x86|INVPCID}}''', {{x86|LahfSahf}},  {{x86|MCOMMIT}}, {{x86|MMX}},  {{x86|MONITOR}}, {{x86|MONITORX}}, {{x86|MOVBE}}, {{x86|MSR}},  {{x86|PCLMULQDQ}}, '''{{x86|PKU}}''', {{x86|POPCNT}}, {{x86|PREFETCH}}, {{x86|RDPID}}, {{x86|RDPRU}}, {{x86|RDRAND}}, {{x86|RDTSCP}}, {{x86|RDSEED}},  {{x86|SHA}},    {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4A}},  {{x86|SSE4.1}}, {{x86|SSE4.2}},  {{x86|SysCallSysRet}}, {{x86|SysEnterSysExit}},  {{x86|TSC}}, '''{{x86|VAES}}''', '''{{x86|VPCLMULQDQ}}''', {{x86|WBNOINVD}},    {{x86|XSAVE}}, {{x86|XSAVEC}}, {{x86|XSAVEOPT}}
-** Security extensions: '''{{x86|CET|CET_SS}}''', {{x86|GMET}}, {{x86|NX}}, {{x86|SME|SEV}}, {{x86|SME|SEV-ES}}, '''{{x86|SME|SEV-SNP}}''', {{x86|SMAP}}, {{x86|SME|SME/TSME}}, {{x86|SMEP}}, {{x86|UMIP}}
-** Speculation control: {{x86|IBPB}}, {{x86|IBRS}}, '''{{x86|PSFD}}''', {{x86|SSBD}}, {{x86|STIBP}}
-* Up to 32 MiB L3 cache per Core Complex (up to 8 CPU cores), 64 to 256 MiB total
-* 8 × 64/72 bit DDR4 SDRAM interface up to 1600 MHz, PC4-25600 (DDR4-3200), 204.8 GB/s
-** Up to 2 DIMMs per channel, 16 total
-** SR/DR RDIMMs, 4R/8R LRDIMMs, 3DS DIMMs, NVDIMMs type N
-** SEC-DED ECC support
-** Up to 4 TiB total
-* Eight 16-lane PCIe Gen 4 (16 GT/s) controllers
-** Configurable x16, x8, x4, x2, x1
-** Up to 8 links per controller
-** SATA, xGMI function on some lanes
-* One 2-lane PCIe Gen 2 controller (WAFL)
-* Four SATA 3.0 (6 Gb/s) controllers, up to 8 lanes each
-* Four USB 1.1/2.0/3.1 (10 Gb/s) ports
-* [[wikipedia:SD card|SD interface]], 6 × [[wikipedia:I%C2%B2C|I2C]], 2 × [[wikipedia:System Management Bus|SMBus]], [[wikipedia:Low Pin Count|LPC]] interface, 4 × [[wikipedia:Universal asynchronous receiver transmitter|UART]], [[wikipedia:Serial Peripheral Interface|SPI/eSPI]], [[wikipedia:General-purpose input/output|GPIO]]
-* {{amd|secure processor|AMD Secure Processor}}, [[Secure Boot]], Hardware root-of-trust
-* TDP range 155 to 280 Watt, configurable
-=== Naming Scheme ===
-{{chip identification
-| title     =
-| parts     = 6
-| ex 1      = EPYC&nbsp;
-| ex 2      = 7
-| ex 3      = 5
-| ex 4      = 5
-| ex 5      = 3
-| ex 6      = P
-| desc 1    = '''Product Family'''
-| desc 2    = <table style="text-align:left"><th colspan="2">Product Series</th>
-<tr><th>7xxx</th><td>High-performance server CPU/SOC</td></tr></table>
-| desc 3    = <table style="text-align:left">
-<th colspan="2">Product Model (Core Count)</th>
-<tr><th>2</th><td>8 cores</td></tr>
-<tr><th>3</th><td>16</td></tr>
-<tr><th>4</th><td>24-28</td></tr>
-<tr><th>5</th><td>32</td></tr>
-<tr><th>6</th><td>40-56</td></tr>
-<tr><th>7</th><td>64 cores</td></tr></table>
-| desc 4    = <table style="text-align:left">
-<th colspan="2">Performance Level</th>
-<tr><th>1</th><td>Value</td></tr>
-<tr><th>4, 5, 6</th><td>Performance</td></tr>
-<tr><th>F</th><td>Frequency optimized and high cache/core ratio,<br/>high performance per core</td></tr></table>
-| desc 5    = <table style="text-align:left">
-<th colspan="2">Generation</th>
-<tr><th>3</th><td>Third generation, 7003 "Milan" series</td></tr></table>
-| desc 6    = <table style="text-align:left">
-<th colspan="2">Feature Modifier</th>
-<tr><th>(none)</th><td>1P, 2P</td></tr>
-<tr><th>P</th><td>1P (single socket) only</td></tr></table>
-}}
-== Milan Processors ==
-<!-- NOTE:
-           This table is generated automatically from the data in the actual articles.
-           If a microprocessor is missing from the list, an appropriate article for it needs to be
-           created and tagged accordingly.
-           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
--->
-{{comp table start}}
-<table class="comptable sortable tc5 tc6">
-{{comp table header|main|10:List of Milan Processors}}
-{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
-{{comp table header|lsep|25:[[Uniprocessors]]}}
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]] [[max cpu count::1]]
- |?full page name
- |?model number
- |?microprocessor family
- |?release price
- |?first launched
- |?core count
- |?thread count
- |?tdp
- |?l2$ size
- |?l3$ size
- |?base frequency#GHz
- |?turbo frequency#GHz
- |format=template
- |template=proc table 3
- |userparam=12
- |mainlabel=-
- |valuesep=,
-}}
-{{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]] [[max cpu count::>>1]]
- |?full page name
- |?model number
- |?microprocessor family
- |?release price
- |?first launched
- |?core count
- |?thread count
- |?tdp
- |?l2$ size
- |?l3$ size
- |?base frequency#GHz
- |?turbo frequency#GHz
- |format=template
- |template=proc table 3
- |userparam=12
- |mainlabel=-
- |valuesep=,
-}}
-{{comp table header|lsep|25:Frequency-optimized SKUs}}
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]] [[part of::Frequency-optimized SKUs]]
- |?full page name
- |?model number
- |?microprocessor family
- |?release price
- |?first launched
- |?core count
- |?thread count
- |?tdp
- |?l2$ size
- |?l3$ size
- |?base frequency#GHz
- |?turbo frequency#GHz
- |format=template
- |template=proc table 3
- |userparam=12
- |mainlabel=-
- |valuesep=,
-}}
-{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Milan]]}}
-</table>
-{{comp table end}}
-=== SKU Comparison ===
-Below are a number of SKU comparison graphs based on their specifications.
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
- |?core count
- |?base frequency
- |charttitle=Cores vs. Base Frequency
- |numbersaxislabel=Frequency (MHz)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
- |?core count
- |?turbo frequency
- |charttitle=Cores vs. Turbo Frequency
- |numbersaxislabel=Frequency (MHz)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
- |?core count
- |?tdp
- |charttitle=Cores vs. TDP
- |numbersaxislabel=TDP (W)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
- |?turbo frequency
- |?tdp
- |charttitle=Frequency vs. TDP
- |numbersaxislabel=TDP (W)
- |labelaxislabel=Frequency (MHz)
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-{{clear}}
-== References ==
-<references/>
-== See also ==
-{{amd zen 3 core see also}}
designer	AMD +
first announced	January 12, 2021 +
first launched	March 15, 2021 +
instance of	core +
isa	x86-64 +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture	Zen 3 +
name	Milan +
package	FCLGA-4094 + and SP3 +
socket	LGA-4094 + and SP3 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +