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|||||Introducing the AMD Opteron™ A1100 for the Datacenter||2016-01||
 
|||||Introducing the AMD Opteron™ A1100 for the Datacenter||2016-01||
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== Graphics Processors ==
 
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!Publ. #!!Rev.!!Title!!Publ. Date!!Notes
 
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|||1.0||[https://developer.amd.com/wordpress/media/2012/10/R3xx_3D_Registers.pdf Radeon R3xx 3D Register Reference Guide]||2008-02-25||9800, 9700, 9600, 9500 series chips
 
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|||1.5||[https://developer.amd.com/wordpress/media/2013/10/R5xx_Acceleration_v1.5.pdf Radeon R5xx Acceleration]||2010-06-08||
 
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|||0.03o||[https://developer.amd.com/wordpress/media/2012/10/RRG-216M56-03oOEM.pdf M56 Register Reference Guide]||2007||AMD R5xx series processors (x1300, x1400, x1600, x1900 series chips)
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/10/R6xx_R7xx_3D.pdf Radeon R6xx/R7xx Acceleration]||2009-04-29||
 
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|||0.37||[https://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf R600-Family Instruction Set Architecture]||2009-01||TeraScale 1 µarch
 
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|42590||1.01o||[https://developer.amd.com/wordpress/media/2012/10/42590_m76_rrg_1.01o.pdf M76 Register Reference Guide]||2007||AMD R6xx series processors (HD2400, HD2600, HD2900 series chips)
 
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|42589||1.01o||[http://developer.amd.com/wordpress/media/2012/10/42589_rv630_rrg_1.01o.pdf RV630 Register Reference Guide]||2007||Register information for AMD R6xx series processors (HD2400, HD2600, HD2900 series chips). This document is generally a subset of the M76 document and has been published for continuity.
 
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|||1.0a||[https://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf R700-Family Instruction Set Architecture Reference Guide]||2011-02||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/10/R6xx_3D_Registers.pdf Radeon R6xx/R7xx 3D Register Reference Guide]||2009-01-26||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/10/evergreen_cayman_programming_guide.pdf Radeon Evergreen/Northern Islands Acceleration]||2011-05-24||
 
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|||1.1a||[https://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf Evergreen Family Instruction Set Architecture]||2011-11||TeraScale 2 µarch
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/10/evergreen_3D_registers_v2.pdf Radeon Evergreen 3D Register Reference Guide]||2011-04-26||
 
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|||1.1||[https://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf HD 6900 Series Instruction Set Architecture]||2011-11||Northern Islands series, TeraScale 3 µarch
 
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|||1.0||[https://www.x.org/docs/AMD/old/cayman_3D_registers_v2.pdf Radeon Cayman 3D Register Reference Guide]||2011-04-26||
 
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|||||[https://web.archive.org/web/20140405160015/https://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf White Paper: AMD Graphics Cores Next (GCN) Architecture]||2012-06||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/10/si_programming_guide_v2.pdf Radeon Southern Islands Acceleration]||2012-04-18||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf Southern Islands Series Instruction Set Architecture]||2012-08||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/10/SI_3D_registers.pdf Radeon Southern Islands 3D/Compute Register Reference Guide]||2011-11-11||
 
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|||1.0||[http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf Sea Islands Series Instruction Set Architecture]||2013-02||GCN 2 µarch
 
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|||1.0||[http://developer.amd.com/wordpress/media/2013/10/CIK_3D_registers_v2.pdf Radeon Sea Islands 3D/Compute Register Reference Guide]||2012-09-19||
 
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|||1.1||[https://developer.amd.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf Graphics Core Next Architecture, Generation 3]||2016-08||Volcanic Islands series ISA
 
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|||||[https://hc27.hotchips.org AMD’s Next Generation GPU and High Bandwidth Memory Architecture: FURY]||2015-08-25||Hot Chips 27
 
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|||||[https://www.amd.com/system/files/documents/polaris-whitepaper.pdf White Paper: Dissecting the Polaris Architecture]||2016||Arctic Islands series
 
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|||||[[:File:vega-whitepaper.pdf|White Paper: Radeon’s next-generation Vega architecture]]||2017||
 
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|||||[https://developer.amd.com/wordpress/media/2017/08/Vega_Shader_ISA_28July2017.pdf “Vega” Instruction Set Architecture Reference Guide]||2017-07-28||
 
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|||||[https://developer.amd.com/wp-content/resources/Vega_7nm_Shader_ISA.pdf “Vega” 7nm Instruction Set Architecture Reference Guide]||2020-01-27||
 
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|||||[https://hc29.hotchips.org AMD’s Radeon Next Generation GPU Architecture “Vega 10”]||2017-08-21||Hot Chips 29
 
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|||||[https://www.amd.com/system/files/documents/rdna-whitepaper.pdf White Paper: Introducing RDNA Architecture]||2019||
 
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|||||[https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf “RDNA 1.0” Instruction Set Architecture Reference Guide]||2020-09-25||Navi 1x series
 
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|||||[https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf “RDNA 2” Instruction Set Architecture]||2020-11-30||Navi 2x series
 
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|||2.03||[http://developer.amd.com/wordpress/media/2012/10/AMD_CAL_Programming_Guide_v2.0.pdf Compute Abstraction Layer (CAL)]||2010-12||
 
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|||2.4||[http://developer.amd.com/wordpress/media/2012/10/AMD_Intermediate_Language_%28IL%29_Specification_v2.pdf AMD Intermediate Language (IL)]||2011-10||
 
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|||2.5||[http://developer.amd.com/wordpress/media/2013/07/AMD_Accelerated_Parallel_Processing_OCL_Programming_Guide-2013-06-21.pdf OpenCL™ Programming Guide]||2013-06||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/12/AMD_OpenCL_Programming_Optimization_Guide.pdf AMD Accelerated Parallel Processing - OpenCL™ Optimization Guide]||2014-12||
 
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|||1.0||[https://developer.amd.com/wordpress/media/2013/12/AMD_OpenCL_Programming_Optimization_Guide2.pdf AMD APP SDK - OpenCL™ Optimization Guide]||2015-08||
 
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|||||[https://hc21.hotchips.org AMD and OpenCL]||2009-08-23||Hot Chips 21
 
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|||||[https://hc24.hotchips.org AMD Radeon™ HD 7970 with Graphics Core Next (GCN) Architecture]||2012-08-28||Hot Chips 24
 
 
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