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Alchemy Au1550-500MBC
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Alchemy Au1550-500MBC
General Info
DesignerAMD
Model NumberAu1550-500MBC
Part NumberAu1550-500MBCAA
MarketEmbedded
IntroductionFebruary 24, 2004 (announced)
May 2004 (launched)
Release Price$33.75 (tray)
ShopAmazon
General Specs
FamilyAlchemy
Frequency500 MHz
Microarchitecture
ISAMIPS32
MicroarchitectureAu1
Core SteppingAA
TechnologyCMOS
Word Size32 bit
Cores1
Max Memory192 MiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.2 V ± 10%
VI/O3.3 V
TDP1440 mW
TDP (Typical)600 mW
Tcase0 °C – 85 °C
Tstorage-40 °C – 125 °C

Au1550-500MBC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by AMD based on earlier Alchemy Semiconductor processors this SoC operates at a base frequency of up to 500 MHz with a typical TDP of 600 mW and maximum TDP of 1440 mW. It was also available as a Pb-free version Au1550-500MBD.

Cache[edit]

Main article: Au1 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
32,768 B
0.0313 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1 × 16 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
1 × 16 KiB4-way set associativewrite-back

Memory controller[edit]

Au1550 processors integrate two independent memory controllers, an SDRAM controller which supports 3.3 V and 2.5 V SDR devices and 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, and I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeSDR-166, DDR-400
Supports ECCNo
Max Mem192 MiB
Controllers1
Channels1
Width16 bit, 32 bit
Max Bandwidth1.333 GB/s
1.241 GiB/s
1,271.248 MiB/s
1,333 MB/s
0.00121 TiB/s
0.00133 TB/s

Expansions[edit]

  • PCI 2.2 controller, 32-bit bus, 33 or 66 MHz
  • USB 1.1 (OHCI) host controller, USB 1.1 device controller with OTG support
    • Two USB host ports and one device port (co-opting a host port in OTG mode)
  • Two 10/100 Mbit/s Ethernet MAC controllers
  • Four Programmable Serial Controllers supporting the AC97, I2S, SPI, and SMBus protocols
  • Three UARTs
  • Up to 43 GPIOs

Graphics[edit]

This processor has no integrated graphics processing unit.

Features[edit]

  • 16-channel descriptor-based DMA controller
    • Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
    • 36-bit source and destination addresses with no alignment requirement
    • Scatter/gather and stride transfers
    • Compare and branch descriptors
  • SafeNet Security Engine to accelerate IP packet encryption/decryption in hardware
    • DES, 3DES, AES, ARC4 encryption algorithms
    • MD5, SHA1 hash algorithms
    • Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets
    • Supports a two-pass hash-then-encrypt implementation of the SSL protocol using either MD5 or SHA1 and 3DES or ARC4 ciphers
    • True entropy-based random number generator
  • RTC and TOY timer
  • Two interrupt controllers
  • Power management unit
  • MIPS EJTAG interface
  • Idle, Sleep, Hibernate Mode

Package[edit]

  • 483-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
  • 25 × 25 grid, 0.8 mm pitch
  • 21 mm × 21 mm × 1.7 mm

Bibliography[edit]

Facts about "Alchemy Au1550-500MBC"
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core steppingAA +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
core voltage tolerance10% +
designerAMD +
familyAlchemy +
first announcedFebruary 24, 2004 +
first launchedMay 2004 +
full page namealchemy/au1550-500mbc +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaMIPS32 +
l1$ size32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
ldateMay 2004 +
market segmentEmbedded +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count1 +
max memory192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth1.241 GiB/s (1,271.248 MiB/s, 1.333 GB/s, 1,333 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureAu1 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberAu1550-500MBC +
nameAlchemy Au1550-500MBC +
part numberAu1550-500MBCAA +
release price$ 33.75 (€ 30.38, £ 27.34, ¥ 3,487.39) +
release price (tray)$ 33.75 (€ 30.38, £ 27.34, ¥ 3,487.39) +
smp max ways1 +
supported memory typeSDR-166 + and DDR-400 +
tdp1.44 W (1,440 mW, 0.00193 hp, 0.00144 kW) +
tdp (typical)0.6 W (600 mW, 8.046e-4 hp, 6.0e-4 kW) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +