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From WikiChip
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- {{intel title|Sandy Bridge (client)|arch}} |designer=Intel84 KB (13,075 words) - 00:54, 29 December 2020
- {{intel title|Skylake (client)|arch}} |designer=Intel79 KB (11,922 words) - 06:46, 11 November 2022
- <!-- Family/Model unknown {{amd|Zen 4|l=arch}} || {{amd|Genoa|l=core}} --> ...ickschur_/status/1296806748267970562--> || Ryzen 5000 APU "{{amd|Cezanne|l=core}}" ({{amd|AM4|l=pack}}, {{amd|FP6|l=pack}})21 KB (3,215 words) - 13:50, 24 July 2023
- {{intel title|Polaris|arch}} |designer=Intel16 KB (2,552 words) - 23:22, 17 May 2019
- {{intel title|Configurable Spatial Accelerator (CSA)}} ...ter]] markets. The CSA is designed to work alongside a traditional [[x86]] core and serve as an [[acceleration engine]].14 KB (2,130 words) - 20:19, 2 October 2018
- {{intel title|Sunny Cove|arch}} |designer=Intel34 KB (5,187 words) - 06:27, 17 February 2023
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