Page title matches

• File:skylake bclk block.png [[Intel]] {{intel|Skylake|l=arch}} BCLK affected blocks. (1,805 × 1,070 (183 KB)) - 03:06, 7 May 2017

Page text matches

• intel/microarchitectures/haswell (client)
  ...28 and 40 [[PCIe]] lanes are possible with a core ratio of up to x80 the [[BCLK]]. [[File:haswell bclk.png|300px|right]]
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...Hz. Note that this has changed from 133 MHz in previous architectures. The BCLK is the reference edge for all the clock domains. Because the core slices an [[File:sandy bridge bclk.png|left|300px]]
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals) ...ocessor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...ocessor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]). * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ...ocessor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]). * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time
  23 KB (3,613 words) - 12:31, 20 June 2021
• intel/turbo boost technology
  ...mit depends on the active core count and the [[microarchitecture]]'s {{x86|BCLK}}. The turbo frequency per each number of active cores is some multiple (ca ! µarch !! {{x86|BCLK}} ||   || µarch !! {{x86|BCLK}}
  7 KB (990 words) - 14:39, 23 July 2022

• File:skylake bclk.png [[Intel]] {{intel|Skylake|l=arch}} BCLK (921 × 1,230 (212 KB)) - 02:39, 7 May 2017

• File:skylake bclk block.png [[Intel]] {{intel|Skylake|l=arch}} BCLK affected blocks. (1,805 × 1,070 (183 KB)) - 03:06, 7 May 2017

• File:haswell bclk.png [[Intell]] {{intel|Haswell|l=arch}} BCLK (995 × 1,265 (249 KB)) - 14:52, 7 May 2017

• intel/microarchitectures/skylake (server)
  ** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals)
  52 KB (7,651 words) - 00:59, 6 July 2022

• File:sandy bridge bclk.png [[Intel]] {{intel|Sandy Bridge}} [[BCLK]] capabilities. Image by Intel. (838 × 991 (480 KB)) - 13:16, 9 September 2017