• intel/crystal well
  '''[[name::Crystal Well]]''' is the [[instance of::codename]] for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris ...two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
  2 KB (371 words) - 02:53, 15 February 2017
• intel/core i7/i7-4950hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  4 KB (404 words) - 16:22, 13 December 2017
• intel/core i7/i7-4960hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (401 words) - 14:24, 12 February 2019
• intel/core i7/i7-4980hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850hq
  ...e [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}. == Cache ==
  3 KB (400 words) - 16:22, 13 December 2017
• intel/core i7/i7-4860hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4870hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (386 words) - 09:14, 26 December 2017
• intel/core i7/i7-4750hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-4760hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (397 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770hq
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (398 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770r
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  4 KB (406 words) - 16:22, 13 December 2017
• intel/core i5/i5-4670r
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  4 KB (404 words) - 16:19, 13 December 2017
• intel/core i5/i5-4570r
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (401 words) - 16:19, 13 December 2017
• intel/core i7/i7-4860eq
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (396 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850eq
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (391 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1284l v3
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (399 words) - 16:27, 13 December 2017
• intel/core i7/i7-5775c
  == Cache == {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
  4 KB (460 words) - 15:03, 24 March 2019
• intel/iris graphics/540
  ...ake U|l=core}}) processors. This GPU incorporates 64 MiB of [[eDRAM]] side cache on-chip for added performance. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}
  4 KB (470 words) - 17:01, 9 July 2017
• intel/iris graphics/550
  ...ake U|l=core}}) processors. This GPU incorporates 64 MiB of [[eDRAM]] side cache on-chip for added performance. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}
  4 KB (475 words) - 06:43, 8 May 2018
• intel/core i3/i3-6167u
  ...emory. The 6167U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (631 words) - 16:18, 13 December 2017
• intel/core i5/i5-6287u
  ...emory. The 6287U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (649 words) - 16:20, 13 December 2017
• intel/microarchitectures/goldmont
  *** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5). ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
  7 KB (956 words) - 23:05, 23 March 2020
• intel/microarchitectures/broadwell (client)
  |l4=128 MiB |l4 per=package
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  |l4=128 MB |l4 per=package
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/skylake (client)
  |side cache=128 MiB |side cache per=package
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  |side cache=64 MiB |side cache per=package
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/core i7/i7-6650u
  ...emory. The 6650U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (649 words) - 16:22, 13 December 2017
• intel/core i7/i7-6660u
  ...emory. The 6660U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (649 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1575m v5
  == Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1545m v5
  == Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1515m v5
  == Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
  4 KB (663 words) - 16:27, 13 December 2017
• intel/iris graphics/pro p580
  ...U incorporating 72 execution units as well as a large 128 MiB [[eDRAM]] of cache. The P580 GPU is found in high-end mobile workstation (Xeon {{intel|Skylake {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}
  4 KB (489 words) - 13:38, 9 July 2017
• intel/microarchitectures/coffee lake
  |l4=128 MiB |l4 per=package
  30 KB (4,192 words) - 13:48, 10 December 2023
• intel/core i3/i3-7167u
  == Cache == {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
  4 KB (636 words) - 16:18, 13 December 2017
• intel/core i5/i5-7287u
  ...1.1 GHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (640 words) - 16:20, 13 December 2017
• intel/core i5/i5-7267u
  ...GHz. This specific GPU also incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (641 words) - 14:22, 16 March 2018
• intel/core i5/i5-7260u
  ...950 MHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (640 words) - 16:20, 13 December 2017
• intel/core i5/i5-7360u
  ...of 1 GHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (640 words) - 07:01, 20 March 2019
• intel/core i7/i7-7560u
  ...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==
  4 KB (647 words) - 16:23, 13 December 2017
• intel/core i7/i7-7567u
  ...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==
  4 KB (647 words) - 16:23, 13 December 2017
• intel/core i7/i7-7660u
  ...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==
  4 KB (647 words) - 23:30, 3 October 2018
• intel/cores/kaby lake u
  ...ntel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache. ...ber">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</
  6 KB (820 words) - 14:10, 29 February 2020
• intel/iris plus graphics 640
  ...IGP offered by Intel with 48 execution units and 64 MiB of dedicated side cache. Iris Plus 640 are found in selected high-end {{intel|Kaby Lake U|l=core}} ...ber">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</
  5 KB (586 words) - 11:52, 6 May 2017
• intel/iris plus graphics 650
  ...IGP offered by Intel with 48 execution units and 64 MiB of dedicated side cache. Iris Plus 650 are found in selected high-end {{intel|Kaby Lake U|l=core}} ...ber">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</
  5 KB (558 words) - 11:52, 6 May 2017
• intel/microarchitectures/gen9.5
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  * Cache * Cache
  14 KB (1,905 words) - 23:38, 22 May 2020
• ibm/microarchitectures/power8
  | cache = Yes | l4 = 128 MiB
  2 KB (217 words) - 15:30, 3 September 2017
• arm/history
  ...corn/microarchitectures/arm3|arm/armv2|arm/armv2a|l1=ARM2|l2=ARM3|l3=ARMv2|l4=ARMv2a}} ...e improvements through a [[process shrink]] and the introduction of on-die cache. Thanks to those improvements, the processor was now capable of running at
  6 KB (834 words) - 01:12, 29 January 2019
• intel/cores/coffee lake u
  ...ors use {{intel|BGA-1356|Socket BGA-1528}} and incorporate 128 MiB of side cache. ** 128 MiB of eDRAM side cache
  4 KB (553 words) - 23:05, 12 May 2020

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