Page title matches

• 128-bit architecture
  ...chitecture that has a [[datapath]] width or a highest [[operand]] width of 128 bits or 16 [[octet]]s. These architectures typically have a matching [[regi ...number of microarchitectures that introduced various extensions to handle 128-bit arithmetic in a more specialized way.
  593 bytes (81 words) - 09:51, 20 July 2018

Page text matches

• mirc/hash tables
  var %hash $calc(($xor(%hash,$calc(%hash /128)) * 9) % 4294967296)
  30 KB (5,149 words) - 01:46, 30 November 2018
• mirc/commands/bread
  * '''-a''' - Modifier for -t switch, codepoints 128-255 are not encoded to UTF8 if no codepoint above 255 is found
  2 KB (366 words) - 22:53, 16 August 2022
• mirc/commands/bset
  ...these last 2 methods do not strictly conform to -ta because they add ASCII 128-255 as single bytes even when codepoint 256+ is present. Also, the last met
  9 KB (1,432 words) - 18:47, 2 May 2023
• mirc/commands/color
  ;Change the color of 1 in the color palette to purple (128, 0, 128). //color 1 $rgb(128,0,128)
  2 KB (255 words) - 22:38, 3 May 2023
• mirc/component object model
  |i1 || single byte signed integer || -128 to 127 |decimal || Holds signed 128-bit (16-byte) values representing 96-bit (12-byte) integer numbers. || +/-7
  27 KB (3,608 words) - 11:41, 25 October 2018
• mirc/commands/colour
  ;Change the color of 1 in the color palette to purple (128, 0, 128). //colour 1 $rgb(128,0,128)
  2 KB (255 words) - 19:13, 15 June 2017
• amd/epyc/9174f
  |pcie lanes=128
  4 KB (693 words) - 01:48, 2 April 2023
• amd/epyc/9224
  |pcie lanes=128
  4 KB (666 words) - 01:48, 2 April 2023
• mirc/identifiers/$decode
  ...-greater that's a multiple of 64, whose UTF8 encoding ends with byte value 128. In these cases, $decode matches the final byte of the message as if it is ...could end with 0x00, or with text strings which could end with byte value 128.
  12 KB (1,991 words) - 09:37, 14 November 2022
• mirc/identifiers/$encode
  ...Parameter#4. Salt is interpreted in ANSI mode without encoding codepoints 128-255 to 2 bytes, and codepoint >255 is an invalid parameter. Warning: $encod ...length 8 if shorter. Parameter#4 is interpreted in ANSI mode, where ASCII 128-255 are not UTF-8 encoded into byte-pairs and codepoint > 255 are invalid.
  33 KB (5,484 words) - 04:32, 16 April 2023
• population count
  ...|| VPOPCNTB/VPOPCNTW || Parallel population count on 8/16-bit operands in 128/256/512-bit vector ...|| VPOPCNTD/VPOPCNTQ || Parallel population count on 32/64-bit operands in 128/256/512-bit vector
  3 KB (447 words) - 01:55, 14 March 2023
• mirc/unicode
  ...: 8 bits can be used to represent 256 values. Code pages all use the first 128 values for ASCII, and then each code page adds the required characters for * 128 - SHIFTJIS_CHARSET
  10 KB (1,506 words) - 10:13, 17 February 2024
• mirc/identifiers/$input
  * '''128''' - show the question icon ('q')
  6 KB (1,062 words) - 07:12, 1 February 2024
• Lists of microprocessors
  ...tecture|60-bit]] - [[64-bit architecture|64-bit]] - [[128-bit architecture|128-bit]] - [[256-bit architecture|256-bit]] - [[512-bit architecture|512-bit]]
  2 KB (248 words) - 23:48, 28 October 2015
• hitachi/hmcs40
  ...arithmetic. 512 to 2,048 Words (10-bit ea) of program [[ROM]]. Additional 128 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM
  4 KB (400 words) - 19:05, 24 May 2016
• national semiconductor/cops ii
  | {{\|COP310C}} || 512 B || 128 b || 4.098 kHz - 62.5 kHz || DIP24 || CMOS, extended temperature version of | {{\|COP311C}} || 512 B || 128 b || 4.098 kHz - 62.5 kHz || DIP16 || CMOS, extended temperature version of
  6 KB (685 words) - 22:49, 5 February 2016
• epson/s1c63
  | package 5 = QFP15-128 | package 8 = TQFP15-128
  5 KB (620 words) - 21:04, 7 February 2016
• number system
  &= 128 + 32 + 8 + 4 + 2 + 0.25 + 0.125 \\
  7 KB (935 words) - 07:08, 2 December 2015
• intel/core i7/i7-4950hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  4 KB (404 words) - 16:22, 13 December 2017
• intel/core i7/i7-4960hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (401 words) - 14:24, 12 February 2019
• intel/core i7/i7-4980hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (400 words) - 16:22, 13 December 2017
• intel/core i7/i7-4860hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4870hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (386 words) - 09:14, 26 December 2017
• intel/core i7/i7-4750hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-4760hq
  ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB
  3 KB (397 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770hq
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (398 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770r
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  4 KB (406 words) - 16:22, 13 December 2017
• intel/core i5/i5-4670r
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  4 KB (404 words) - 16:19, 13 December 2017
• intel/core i5/i5-4570r
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (401 words) - 16:19, 13 December 2017
• intel/core i7/i7-4860eq
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (396 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850eq
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (391 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1284l v3
  ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB
  3 KB (399 words) - 16:27, 13 December 2017
• intel/celeron/3855u
  |l1 cache=128 KiB
  4 KB (596 words) - 16:15, 13 December 2017
• intel/celeron/3955u
  |l1 cache=128 KiB
  4 KB (596 words) - 16:15, 13 December 2017
• intel/core i3/i3-6098p
  |l1 cache=128 KiB
  4 KB (627 words) - 16:17, 13 December 2017
• intel/core i5/i5-6402p
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (627 words) - 16:20, 13 December 2017
• intel/core i7/i7-6498du
  |l1 cache=128 KiB
  4 KB (640 words) - 02:21, 16 January 2019
• intel/core i5/i5-6198du
  |l1 cache=128 KiB
  4 KB (650 words) - 02:21, 16 January 2019
• intel/iris pro graphics 5200
  ...tegrated graphic processors with an additional L4$ of {{intel|crystal well|128 MB eDRAM}}.
  2 KB (300 words) - 19:39, 3 January 2016
• intel/core i7/i7-5950hq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (407 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850hq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850eq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (395 words) - 16:22, 13 December 2017
• intel/core i7/i7-5750hq
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (424 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775r
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (405 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775c
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (460 words) - 15:03, 24 March 2019
• intel/core i5/i5-5675r
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5675c
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (454 words) - 18:17, 2 November 2019
• intel/core i5/i5-5575r
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5350h
  |l1i cache=128 KiB |l1d cache=128 KiB
  4 KB (415 words) - 16:19, 13 December 2017

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