• intel/microarchitectures/bonnell
  ...ly, manufacturers were allowed to use the '''Centrino Atom''' brand if the system consist of a Bonnell-based processor, the chipset, wireless capabilities ([ ...ase in the world, including the ability to run any other [[x86]] operating system unmodified. At the same time it forced the design team to resort to other m
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures
  ...C|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustaine
  3 KB (384 words) - 20:59, 8 February 2022
• intel/microarchitectures/sandy bridge (client)
  ...on versus its {{intel|microarchitectures|predecessors}} resulting a full [[system on a chip]] design. * New {{intel|System Agent}} architecture
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  * [[System Agent]] ** System [[DRAM]]:
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ** System [[DRAM]]: * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual [[FSB]] sp
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ...onnect architecture}} along with {{\\|Gen11}} GPU, and an improved {{intel|System Agent}} with a new display engine and I/O. ...{{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The
  23 KB (3,613 words) - 12:31, 20 June 2021
• x86/umip
  ...a general purpose register. These instructions are intended for operating system use and date back to the Intel {{intel|80286}} microarchitecture. SMSW was ...in turn point to interrupt handler code. CR0 contains flags which control operating modes of the processor. User-mode code was never able to load values into t
  2 KB (338 words) - 01:25, 30 December 2019
• intel/turbo boost technology
  ...bo Boost and have the feature enabled and supported (e.g. most [[operating system|OSs]]). Under various workloads, especially ones that are relatively low in ...bled or enabled. Additionally, Turbo Boosts operates under the [[operating system]]'s control and is engaged automatically when the OS requests the highest p
  7 KB (990 words) - 14:39, 23 July 2022
• intel/80486/486dx2-40
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). * {{intel|System Management Mode}} (SMM)
  2 KB (240 words) - 16:13, 13 December 2017
• intel/80486/486dx2-50
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). * {{intel|System Management Mode}} (SMM)
  3 KB (345 words) - 16:13, 13 December 2017
• intel/80486/486dx2-66
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). * {{intel|System Management Mode}} (SMM)
  4 KB (372 words) - 06:28, 15 February 2024
• intel/80486/486dx4-75
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as th * {{intel|System Management Mode}} (SMM)
  3 KB (354 words) - 16:13, 13 December 2017
• intel/80486/486dx4-100
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as th * {{intel|System Management Mode}} (SMM)
  4 KB (414 words) - 16:13, 13 December 2017
• intel/80486/486sx2-50
  ...el|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX * {{intel|System Management Mode}} (SMM)
  2 KB (253 words) - 16:14, 13 December 2017
• intel/80486/486sx2-66
  ...el|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 66 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX * {{intel|System Management Mode}} (SMM)
  2 KB (220 words) - 16:14, 13 December 2017
• amd/am5x86/am486dx5-133w16bhc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (324 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133w16bgc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (358 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133v16bhc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (342 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133v16bgc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (337 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133adw
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (336 words) - 15:19, 13 December 2017

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