Page title matches

Page text matches

• intel/xeon e3/e3-1575m v5
  |mcp=Yes
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1545m v5
  |mcp=Yes
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1515m v5
  |mcp=Yes
  4 KB (663 words) - 16:27, 13 December 2017
• intel/pentium (2009)/4405y
  |mcp=Yes
  4 KB (581 words) - 17:57, 28 August 2018
• intel/pentium (2009)/4405u
  |mcp=Yes
  4 KB (597 words) - 16:25, 13 December 2017
• intel/core m/m7-6y75
  |mcp=Yes
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core m/m5-6y54
  |mcp=Yes
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core m/m5-6y57
  |mcp=Yes
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core m/m3-6y30
  |mcp=Yes
  4 KB (613 words) - 17:58, 28 August 2018
• intel/core i3/i3-6100u
  |mcp=Yes
  4 KB (616 words) - 16:17, 13 December 2017
• amd/microarchitectures/zen
  ===== 2-die MCP ===== 2-die MCP used for {{amd|Threadripper}}:
  79 KB (12,095 words) - 15:27, 9 June 2023
• intel/core i3/i3-6006u
  |mcp=Yes
  5 KB (687 words) - 02:21, 16 January 2019
• intel/cores/kaby lake y
  ...ckaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies are done via a lightweight On-Pac
  4 KB (594 words) - 06:30, 6 April 2019
• intel/cores/kaby lake u
  ...ckaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip conf
  6 KB (820 words) - 14:10, 29 February 2020
• amd/epyc/7f32
  |mcp=Yes
  3 KB (563 words) - 11:06, 15 April 2020
• heterogeneous integration
  * [[Multi-Chip Package]] (MCP) is a package that incorporates multiple dice together with die-to-die inte
  1 KB (173 words) - 20:47, 7 November 2017
• intel/cores/coffee lake u
  ...ckaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP) along with the [[eDRAM]]. Communication between the separate dies are done
  4 KB (553 words) - 23:05, 12 May 2020
• intel/cores/skylake y
  ...ckaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies are done via a lightweight On-Pac
  4 KB (571 words) - 06:30, 6 April 2019
• amd/epyc/7351p
  |mcp=Yes
  3 KB (531 words) - 12:24, 18 March 2023
• amd/epyc/7401p
  |mcp=Yes
  4 KB (557 words) - 12:26, 18 March 2023

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