• intel/core i5/i5-6287u
  ...emory. The 6287U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (649 words) - 16:20, 13 December 2017
• intel/microarchitectures/goldmont
  *** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5). ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
  7 KB (956 words) - 23:05, 23 March 2020
• intel/microarchitectures/broadwell (client)
  |l4=128 MiB |l4 per=package
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  |l4=128 MB |l4 per=package
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/skylake (client)
  |side cache=128 MiB |side cache per=package
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  |side cache=64 MiB |side cache per=package
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/core i7/i7-6650u
  ...emory. The 6650U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (649 words) - 16:22, 13 December 2017
• intel/core i7/i7-6660u
  ...emory. The 6660U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (649 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1575m v5
  == Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1545m v5
  == Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
  4 KB (654 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1515m v5
  == Cache == {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
  4 KB (663 words) - 16:27, 13 December 2017
• intel/iris graphics/pro p580
  ...U incorporating 72 execution units as well as a large 128 MiB [[eDRAM]] of cache. The P580 GPU is found in high-end mobile workstation (Xeon {{intel|Skylake {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}
  4 KB (489 words) - 13:38, 9 July 2017
• intel/microarchitectures/coffee lake
  |l4=128 MiB |l4 per=package
  30 KB (4,192 words) - 13:48, 10 December 2023
• intel/core i3/i3-7167u
  == Cache == {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
  4 KB (636 words) - 16:18, 13 December 2017
• intel/core i5/i5-7287u
  ...1.1 GHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (640 words) - 16:20, 13 December 2017
• intel/core i5/i5-7267u
  ...GHz. This specific GPU also incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (641 words) - 14:22, 16 March 2018
• intel/core i5/i5-7260u
  ...950 MHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (640 words) - 16:20, 13 December 2017
• intel/core i5/i5-7360u
  ...of 1 GHz. This specific GPU incorporates an additional 64 MiB of [[eDRAM]] L4$. == Cache ==
  4 KB (640 words) - 07:01, 20 March 2019
• intel/core i7/i7-7560u
  ...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==
  4 KB (647 words) - 16:23, 13 December 2017
• intel/core i7/i7-7567u
  ...GHz. This particular [[GPU]] includes an additional 64 MiB of [[eDRAM]] [[L4$]]. == Cache ==
  4 KB (647 words) - 16:23, 13 December 2017

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