Page title matches

Page text matches

• intel/core i5/i5-6402p
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (627 words) - 16:20, 13 December 2017
• intel/core i7/i7-6498du
  |l1i cache=64 KiB |l1i break=2x32 KiB
  4 KB (640 words) - 02:21, 16 January 2019
• intel/core i5/i5-6198du
  |l1i cache=64 KiB |l1i break=2x32 KiB
  4 KB (650 words) - 02:21, 16 January 2019
• intel/core i7/i7-5500du
  |l1i cache=64 KiB |l1i break=2x32 KiB
  5 KB (469 words) - 16:22, 13 December 2017
• intel/core i7/i7-5950hq
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (407 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850hq
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850eq
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (395 words) - 16:22, 13 December 2017
• intel/core i7/i7-5750hq
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (424 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775r
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (405 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775c
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (460 words) - 15:03, 24 March 2019
• intel/core i5/i5-5675r
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5675c
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (454 words) - 18:17, 2 November 2019
• intel/core i5/i5-5575r
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5350h
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (415 words) - 16:19, 13 December 2017
• intel/core i3/i3-6167u
  |l1i cache=64 KiB |l1i break=2x32 KiB
  4 KB (631 words) - 16:18, 13 December 2017
• intel/core i5/i5-6287u
  |l1i cache=64 KiB |l1i break=2x32 KiB
  4 KB (649 words) - 16:20, 13 December 2017
• Property:l1i$ size
  This is a '''[[has type::quantity]]''' property representing the size of the L1i$ of a microprocessor. '''This property adheres to the [[WikiChip:data size
  372 bytes (52 words) - 22:13, 27 May 2021
• baikal/baikal-t1
  |l1i cache=64 KiB |l1i break=2x32 KiB
  3 KB (323 words) - 16:10, 13 December 2017
• intel/atom x7/z8750
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (462 words) - 16:15, 13 December 2017
• intel/atom x7/z8700
  |l1i cache=128 KiB |l1i break=4x32 KiB
  4 KB (472 words) - 16:15, 13 December 2017

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