The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. Mass production of [[integrated circuit]] fabricated using a 7 nm process began in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the [[5 nm node]].

First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 50s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't.  

now four companies are currently planning or developing a 7-nanometer node: [[Intel]], [[TSMC]], [[Samsung]] and [[SMIC]].

==== Intel 7 ====

===== Intel 7 Ultra =====

[[File:raptor-lake-v-f-curve-improvements.png|thumb|right|New V-F Curve for the Enhanced Intel 7 process.]]

Intel introduced an '''enhanced version of the Intel 7 process''' in late 2022 with the introduction of the company's 13th Generation Core processors based on the {{intel|Raptor Lake|l=arch}} microarchitecture. Nicknamed '''"Intel 7 Ultra"''' internally, the new process is a full PDK update over the one used by Alder Lake, their 3rd generation SuperFin Transistor architecture. Intel says this process brings transistors with significantly better channel mobility. At the very high end of the V-F curve, the company says peak frequency is nearly 1 GHz higher now. The curve itself has been improved, shifting prior-generation frequencies by around 200 MHz at ISO-voltage, or alternatively, reducing the voltage by over 50 mV at ISO-frequency.

TSMC 7-nanometer (N7 and N7P are the same with this regard) comes in two variations - high density and high performance. Those [[standard cell|cells]] are 240 nm and 300 nm tall respectively. Prior to full production ramp, TSMC originally had a 9T HP variant that relied on a 57-nm CPP. That library was eventually obsoleted in favor of a 64-nm CPP 7.5T library which is now used in mass production by various companies. Note that the 7.5T and 9T are similar in power and performance. Some early designs that started out with a 9T library continued to use it regardless.

<tr><th>Type</th><th>High Density</th><th colspan="2">High Performance</th></tr>

<tr><th>Name</th><td>H240 HD</td><td>H300 HP</td><td style="text-decoration:line-through">H360 HP</td></tr>

<tr><th>Fin Pitch</th><td colspan="3">30 nm</td></tr>

<tr><th>Metal</th><td colspan="3">40 nm (smallest pitch used with DP)<br>76 nm (smallest pitch used with SP)</td></tr>

<tr><th>Gate Pitch</th><td>57 nm</td><td>64 nm</td><td style="text-decoration:line-through">57 nm</td></tr>

<tr><th>Height</th><td>240 nm<br>8-fin x 30 nm</td><td>300 nm<br>10-fin x 30 nm</td><td style="text-decoration:line-through">360 nm<br>12-fin x 30 nm</td></tr>

<tr><th>Tracks</th><td>6 T</td><td>7.5 T</td><td style="text-decoration:line-through">9 T</td></tr>

[[File:vlsi-2019-n7p-2nd-gen-perf.png|200px|thumb|right|N7P (2nd Gen) vs N7 (1st Gen) improvements. (VLSI 2019)]]

The '''N7+ node''' is TSMC's first process technology to adopt [[EUV lithography]]. It is unrelated to both the N7 and N7P processes, and is not IP-compatible with either, requiring re-implementation (new physical layout and validation). N7+ entered mass production in the second quarter of 2019 and uses EUV for four critical layers. Compared to TSMC N7 process, N7+ is said to deliver around 1.2x density improvement. N7+ is also said to deliver 10% higher performance at iso-power or, alternatively, up to 15% lower power at iso-performance. On paper, N7+ appears to be marginally better than N7P, albeit that comes at the cost of re-implementing the design.

** {{hisilicon|kirin|990 4G/5G}}