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{{lithography processes}}
 
{{lithography processes}}
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The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. Mass production of [[integrated circuit]] fabricated using a 7 nm process began in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the [[5 nm node]].
+
The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology and does not represent any geometry of a transistor. Commercial mass production of [[integrated circuit]] using 7 nm process is started in 2018. This technology will be replaced by [[5 nm lithography process|5 nm process]] around 2020/21.
  
−
The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
+
== Industry ==
 +
Only four semiconductor foundries are able to develop the advanced 7nm: [[Intel]], [[Samsung]], [[TSMC]], and [[GlobalFoundries]].
  
−
== Overview ==
+
{{future information}}
−
First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 50s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't.
 
  
−
=== Density ===
 
−
In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90-102 million [[transistors per square millimeter]] based on WikiChip's own analysis.
 
  
−
:[[File:7nm densities.svg|700px]]
+
{{finfet nodes comp
 +
<!-- Intel -->
 +
| process 1 fab          = [[Intel]]
 +
| process 1 name        = P1276 (CPU), P1277 (SoC)
 +
| process 1 date        = &nbsp;
 +
| process 1 lith        = EUV
 +
| process 1 immersion    = &nbsp;
 +
| process 1 exposure    = &nbsp;
 +
| process 1 wafer type  = Bulk
 +
| process 1 wafer size  = 300 mm
 +
| process 1 transistor  = &nbsp;
 +
| process 1 volt        = &nbsp;
 +
| process 1 delta from  = [[10 nm]] Δ
 +
| process 1 fin pitch    = &nbsp;
 +
| process 1 fin pitch Δ  = &nbsp;
 +
| process 1 fin width    = &nbsp;
 +
| process 1 fin width Δ  = &nbsp;
 +
| process 1 fin height  = &nbsp;
 +
| process 1 fin height Δ = &nbsp;
 +
| process 1 gate len    = &nbsp;
 +
| process 1 gate len Δ  = &nbsp;
 +
| process 1 cpp          = &nbsp;
 +
| process 1 cpp Δ        = &nbsp;
 +
| process 1 mmp          = &nbsp;
 +
| process 1 mmp Δ        = &nbsp;
 +
| process 1 sram hp      = &nbsp;
 +
| process 1 sram hp Δ    = &nbsp;
 +
| process 1 sram hd      = &nbsp;
 +
| process 1 sram hd Δ    = &nbsp;
 +
| process 1 sram lv      = &nbsp;
 +
| process 1 sram lv Δ    = &nbsp;
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = &nbsp;
 +
<!-- TSMC -->
 +
| process 2 fab          = [[TSMC]]
 +
| process 2 name        = 7FF, 7FF+<info>will use EUVL instead of immersion lithography</info>, 7HPC
 +
| process 2 date        = Q1, 2018
 +
| process 2 lith        = 193 nm
 +
| process 2 immersion    = Yes
 +
| process 2 exposure    = SAQP
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = 300 mm
 +
| process 2 transistor  = FinFET
 +
| process 2 volt        = 0.70 V
 +
| process 2 delta from  = [[10 nm]] Δ
 +
| process 2 fin pitch    = &nbsp;
 +
| process 2 fin pitch Δ  = &nbsp;
 +
| process 2 fin width    = &nbsp;
 +
| process 2 fin width Δ  = &nbsp;
 +
| process 2 fin height  = &nbsp;
 +
| process 2 fin height Δ = &nbsp;
 +
| process 2 gate len    = &nbsp;
 +
| process 2 gate len Δ  = &nbsp;
 +
| process 2 cpp          = 54 nm
 +
| process 2 cpp Δ        = 0.84x
 +
| process 2 mmp          = 40 nm
 +
| process 2 mmp Δ        = 0.95x
 +
| process 2 sram hp      = &nbsp;
 +
| process 2 sram hp Δ    = &nbsp;
 +
| process 2 sram hd      = 0.027 µm²
 +
| process 2 sram hd Δ    = 0.64x
 +
| process 2 sram lv      = &nbsp;
 +
| process 2 sram lv Δ    = &nbsp;
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = &nbsp;
 +
<!-- GlobalFoundries -->
 +
| process 3 fab          = [[GlobalFoundries]]
 +
| process 3 name        = 7LP<info>7nm Leading Performance</info>
 +
| process 3 date        = 2019
 +
| process 3 lith        = 193 nm
 +
| process 3 immersion    = Yes
 +
| process 3 exposure    = SAQP
 +
| process 3 wafer type  = Bulk
 +
| process 3 wafer size  = 300 mm
 +
| process 3 transistor  = FinFET
 +
| process 3 volt        = 0.70 V
 +
| process 3 delta from  = [[14 nm]] Δ
 +
| process 3 fin pitch    = 30 nm
 +
| process 3 fin pitch Δ  = 0.63x
 +
| process 3 fin width    = &nbsp;
 +
| process 3 fin width Δ  = &nbsp;
 +
| process 3 fin height  = &nbsp;
 +
| process 3 fin height Δ = &nbsp;
 +
| process 3 gate len    = &nbsp;
 +
| process 3 gate len Δ  = &nbsp;
 +
| process 3 cpp          = 56 nm
 +
| process 3 cpp Δ        = 0.72x
 +
| process 3 mmp          = 40 nm
 +
| process 3 mmp Δ        = 0.63x
 +
| process 3 sram hp      = 0.0353 µm²
 +
| process 3 sram hp Δ    = 0.44x
 +
| process 3 sram hd      = 0.0269 µm²
 +
| process 3 sram hd Δ    = 0.42x
 +
| process 3 sram lv      = &nbsp;
 +
| process 3 sram lv Δ    = &nbsp;
 +
| process 3 dram        = &nbsp;
 +
| process 3 dram Δ      = &nbsp;
 +
<!-- Samsung -->
 +
| process 4 fab          = [[Samsung]]
 +
| process 4 name        = 7LPE<info>7 nm Low Power Early</info>
 +
| process 4 date        = 2019
 +
| process 4 lith        = EUV
 +
| process 4 immersion    = &nbsp;
 +
| process 4 exposure    = SE
 +
| process 4 wafer type  = Bulk
 +
| process 4 wafer size  = 300 mm
 +
| process 4 transistor  = FinFET
 +
| process 4 volt        = &nbsp;
 +
| process 4 delta from  = [[10 nm]] Δ
 +
| process 4 fin pitch    = &nbsp;
 +
| process 4 fin pitch Δ  = &nbsp;
 +
| process 4 fin width    = &nbsp;
 +
| process 4 fin width Δ  = &nbsp;
 +
| process 4 fin height  = &nbsp;
 +
| process 4 fin height Δ = &nbsp;
 +
| process 4 gate len    = &nbsp;
 +
| process 4 gate len Δ  = &nbsp;
 +
| process 4 cpp          = 54 nm
 +
| process 4 cpp Δ        = 0.79x
 +
| process 4 mmp          = 36 nm
 +
| process 4 mmp Δ        = 0.7x
 +
| process 4 sram hp      = &nbsp;
 +
| process 4 sram hp Δ    = &nbsp;
 +
| process 4 sram hd      = 0.0260 µm²
 +
| process 4 sram hd Δ    = 0.65x
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;
 +
<!-- Common Platform -->
 +
| process 5 fab          = Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> Paper
 +
| process 5 name        = &nbsp;
 +
| process 5 date        = &nbsp;
 +
| process 5 lith        = EUV
 +
| process 5 immersion    = &nbsp;
 +
| process 5 exposure    = SE
 +
| process 5 wafer type  = Bulk
 +
| process 5 wafer size  = 300 nm
 +
| process 5 transistor  = FinFet
 +
| process 5 volt        = &nbsp;
 +
| process 5 delta from  = [[10 nm]] Δ
 +
| process 5 fin pitch    = &nbsp;
 +
| process 5 fin pitch Δ  = &nbsp;
 +
| process 5 fin width    = &nbsp;
 +
| process 5 fin width Δ  = &nbsp;
 +
| process 5 fin height  = &nbsp;
 +
| process 5 fin height Δ = &nbsp;
 +
| process 5 gate len    = &nbsp;
 +
| process 5 gate len Δ  = &nbsp;
 +
| process 5 cpp          = 48 nm
 +
| process 5 cpp Δ        = 0.75x
 +
| process 5 mmp          = 36 nm
 +
| process 5 mmp Δ        = 0.75x
 +
| process 5 sram hp      = &nbsp;
 +
| process 5 sram hp Δ    = &nbsp;
 +
| process 5 sram hd      = &nbsp;
 +
| process 5 sram hd Δ    = &nbsp;
 +
| process 5 sram lv      = &nbsp;
 +
| process 5 sram lv Δ    = &nbsp;
 +
| process 5 dram        = &nbsp;
 +
| process 5 dram Δ      = &nbsp;
 +
}}
  
−
== Industry ==
+
=== Intel ===
−
now four companies are currently planning or developing a 7-nanometer node: [[Intel]], [[TSMC]], [[Samsung]] and [[SMIC]].
+
* '''Note:'''  For the most part, foundries' 7nm process is competing against [[10_nm_lithography_process#Intel|Intel's 10nm process]], not their 7nm.
 +
 +
On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel's 7 nm node has entered development phase and that the company's research focuses on the [[5 nm]] and [[3 nm]] nodes. Details of their 7 nm node have not been disclosed yet. CEO Brian Krzanich mentioned a 2020 timeframe in an investor conference in June.
  
−
{{node comp|node=7 nm}}
+
=== GlobalFoundries ===
 +
[[File:globalfoundries interconnect 7nm.jpg|right|350px]]
 +
On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of [[EUV]], the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.
  
−
=== Intel ===
+
The 7nm process features SAQP for the FEOL, and double patterning for the BEOL. GlobalFoundries claims a 2.8 times density improvement compared to their 14nm process, and a performance improvement of 40% or a 55% reduction in power consumption. Two versions of the process will be developed: a low power version for mobile applications. And a high performance version for desktop and server chips.
−
==== Intel 7 ====
 
−
===== Intel 7 Ultra =====
 
−
[[File:raptor-lake-v-f-curve-improvements.png|thumb|right|New V-F Curve for the Enhanced Intel 7 process.]]
 
−
Intel introduced an '''enhanced version of the Intel 7 process''' in late 2022 with the introduction of the company's 13th Generation Core processors based on the {{intel|Raptor Lake|l=arch}} microarchitecture. Nicknamed '''"Intel 7 Ultra"''' internally, the new process is a full PDK update over the one used by Alder Lake, their 3rd generation SuperFin Transistor architecture. Intel says this process brings transistors with significantly better channel mobility. At the very high end of the V-F curve, the company says peak frequency is nearly 1 GHz higher now. The curve itself has been improved, shifting prior-generation frequencies by around 200 MHz at ISO-voltage, or alternatively, reducing the voltage by over 50 mV at ISO-frequency.
 
  
 
=== TSMC ===
 
=== TSMC ===
−
TSMC started mass production of its '''7-nanometer N7 node''' in April 2018. TSMC considers its 7-nanometer node a full node shrink over its 16-nanometer. Although TSMC has released a 10-nanometer node the year prior, the company considered its 10 nm to be a short-lived node and was intended to serve as a learning node on its way to 7. In early 2019 TSMC introduced the second version of its N7 process called '''N7P''' which provides additional performance enhancements. With the availability of [[asml/nxe|high-throughput EUV machines]] ready for mass production, TSMC introduced a third variant called '''N7+''' which uses EUV.
+
[[File:7nm tsmc.jpeg|right|200px]]
−
 
+
In ISSCC 2017, the memory group at [[TSMC]] detailed their test 256 Mib SRAM chip which featured a 42.64 mm² die. The chip is manufactured on TSMC's 7nm HK-MG FinFET process using SAQP. The over die is 0.34x smaller than their [[16 nm process]] version. TSMC's 7nm process density is 1.6X compared to their 10nm process. Minimum metal pitch is 40 nm, as reported at IEDM 2016. TSMC claims their 7nm process will deliver a 20% performance improvement and a 40% reduction in power consumption.  
−
==== N7 ====
 
−
[[File:n7_overview_slide.jpg|right|thumb|N7 Overview]]
 
−
TSMC original '''7-nanometer N7 process''' was introduced in April 2018. Compared to its own [[16-nanometer technology]], TSMC claims its 7 nm node provides around 35-40% speed improvement or 65% lower power. Compared to the half-node [[N10|10 nm node]], N7 is said to provide ~20% speed improvement or ~40% power reduction. In terms of density, N7 is said to deliver 1.6x and 3.3x improvement compared to [[N10]] and [[N16]] respectively. N7 largely builds on all prior FinFET processes the company has had previously. To that end, this is a fourth-generation [[FinFET]], fifth-generation [[HKMG]], gate-last, dual gate oxide process.
 
−
 
 
−
{| class="wikitable" style="text-align: center;"
 
−
|-
 
−
! colspan="3" | N7 [[PPA]] vs. [[N16]]
 
−
|-
 
−
! Speed @ iso-power !! Power @ iso-speed !! Density
 
−
|-
 
−
| ~30% || ~55% || ~3.3x
 
−
|-
 
−
! colspan="3" | N7 PPA vs. [[N10]]
 
−
|-
 
−
! Speed @ iso-power !! Power @ iso-speed !! Density
 
−
|-
 
−
| ~20% || ~40% || ~1.6x
 
−
|}
 
  
−
[[File:tsmc-weff-16-10-7.svg|thumb|right|W<sub>eff</sub> for TSMC [[N16|16]], [[N10|10]], and 7 nm.]]
+
The 7nm node will come in two variants, one optimized for mobile applications and a second one optimized for High performance applications.
−
For N7, TSMC continued to use [[deep ultraviolet]] (DUV) 193 nm ArF Immersion lithography. The limitations of i193 dictated some of the design rules for the process. For the transistor, the gate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the [[SADP]] point. Design rules were carefully made to stay within double patterning. Single patterning was pushed slightly further to the 76 nanometers point. The design rules for N7 are shown below.
+
TSMC plans to introduce a second improved process called 7nm+ a year later, which will introduce some layers processed with EUVL. This will improve yields and reduce fab cycle times. The 7nm+ process will deliver improved power consumption and between 15-20% area scaling over their first generation 7nm process.
  
−
{| class="wikitable" style="text-align: center;"
+
{| class="collapsible collapsed wikitable"
−
! colspan="4" | TSMC N7 Design Rules
 
−
|-
 
−
! Layer !! Pitch (nm) !! Patterning !! Notes
 
−
|-
 
−
| Fin || 30 || SAQP ||
 
−
|-
 
−
| Poly || 57 || SADP ||
 
−
|-
 
−
| M0 || 40 || SADP || Mx
 
−
|-
 
−
| M1 || 40 || SADP || 1x
 
−
|-
 
−
| M2 || 40 || SADP || 1x
 
−
|-
 
−
| M3 || 40 || SADP || 1x
 
−
|-
 
−
| M4 || 40 || SADP || 1x
 
−
|-
 
−
| M5 || 76 || Single || 1.9x
 
−
|-
 
−
| M6 || 76 || Single || 1.9x
 
−
|-
 
−
| M7 || 76 || Single || 1.9x
 
−
|-
 
−
| M8 || 76 || Single || 1.9x
 
−
|-
 
−
| M9 || 76 || Single || 1.9x
 
 
|-
 
|-
−
| M10 || 124 || Single || 3.1x
+
! colspan="2" | TSMC 256 Mib SRAM demo 7 nm wafer
 
|-
 
|-
−
| M11, M12 || 720 || Single || 18x
+
|
−
|}
+
<table class="wikitable">
−
 
+
<tr><th>Technology</th><td>7 nm HK-MG FinFET</td></tr>
−
It's worth pointing out that the aggressive [[fin pitch]] scaling have resulted in a fairly dense [[SRAM bitcells]]. The N7 high-density [[SRAM bitcell]] is 0.027 µm².
+
<tr><th>Metal scheme</th><td>1 Poly  / 7 Metal</td></tr>
−
 
+
<tr><th>Supply voltage</th><td>0.75 V (core)<br>1.8 V (i/o)</td></tr>
−
[[File:mss-n7-a12.jpg|right|thumb|Elements distribution of Apple's A12 SoC (MSS Corp). Cobalt contacts can be seen.]]
+
<tr><th>Bit cell size</th><td>0.027 µm²</td></tr>
−
The transistor profile has been enhanced as well. Like [[Intel's 10 nm process]], TSMC introduced cobalt fill at the [[trench contacts]], replacing the tungsten contact. This has the effect of reducing the resistance in that area by 50%. Some of the area scaling and cost benefits were achieved through [[fin pitch]]/[[fin height|height]] [[scaling]]. Continuing to scale the fin width gives you a narrower channel while increasing the height to maintain a good effective width is done in order to improve the short channel characteristics and [[subthreshold slope]] (i.e., improved Ieff / Ceff) but it also degrades the overall parasitics. Keep in mind that overall, the CV/I [[device delay]] is still better because the [[intrinsic capacitance]] like the [[Cgate]] and [[Cov]] still scale with [[Ieff]].
+
<tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr>
−
 
+
<tr><th>Capacity</th><td>256 Mib</td></tr>
−
Another way to visualize the effect of the width and height scaling is through the effective width. In the graph shown on the left, we plotted the effective width from TSMC 16 nanometer to the current 7-nanometer node. Compared to [[N16]], N7 has over twice the effective channel width.
+
<tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr>
−
 
+
<tr><th>Die Size</th><td>5903 µm x 7223 µm = 42.64 mm²</td></tr>
−
Different multi-Vt devices were developed for this process with a Vt range of around 200 mV.
 
−
 
 
−
===== Std Cells =====
 
−
TSMC 7-nanometer (N7 and N7P are the same with this regard) comes in two variations - high density and high performance. Those [[standard cell|cells]] are 240 nm and 300 nm tall respectively. Prior to full production ramp, TSMC originally had a 9T HP variant that relied on a 57-nm CPP. That library was eventually obsoleted in favor of a 64-nm CPP 7.5T library which is now used in mass production by various companies. Note that the 7.5T and 9T are similar in power and performance. Some early designs that started out with a 9T library continued to use it regardless.
 
−
 
 
−
<table class="wikitable" style="text-align: center;">
 
−
<tr><th>Type</th><th>High Density</th><th colspan="2">High Performance</th></tr>
 
−
<tr><th>Name</th><td>H240 HD</td><td>H300 HP</td><td style="text-decoration:line-through">H360 HP</td></tr>
 
−
<tr><th>Fin Pitch</th><td colspan="3">30 nm</td></tr>
 
−
<tr><th>Metal</th><td colspan="3">40 nm (smallest pitch used with DP)<br>76 nm (smallest pitch used with SP)</td></tr>
 
−
<tr><th>Gate Pitch</th><td>57 nm</td><td>64 nm</td><td style="text-decoration:line-through">57 nm</td></tr>
 
−
<tr><th>Height</th><td>240 nm<br>8-fin x 30 nm</td><td>300 nm<br>10-fin x 30 nm</td><td style="text-decoration:line-through">360 nm<br>12-fin x 30 nm</td></tr>
 
−
<tr><th>Tracks</th><td>6 T</td><td>7.5 T</td><td style="text-decoration:line-through">9 T</td></tr>
 
 
</table>
 
</table>
−
 
+
| [[File:tsmc 7nm SRAM block.png]]
−
[[File:n7_cell_height.svg|500px]]
 
−
[[File:sdm855-n7-hd-hp-ieff.png|thumb|right|Qualcomm's [[Snapdragon 855]] [[Ieff]] difference between the HD and HP cells. (VLSI 2019)]]
 
−
Qualcomm reported that on its own SoC ([[Snapdragon 855]]), the high-performance cells deliver around 10-13% higher effective drive current ([[Ieff]]), albeit at the cost of being slightly leakier transistors. Based on WikiChip's own analysis, the dense cells come at around 91.2 [[MTr/mm²]] while the less dense, high-performance cells, are calculated at around 65 MTr/mm².
 
−
 
 
−
{{clear}}
 
−
 
 
−
==== N7P ====
 
−
[[File:vlsi-2019-n7p-2nd-gen-perf.png|200px|thumb|right|N7P (2nd Gen) vs N7 (1st Gen) improvements. (VLSI 2019)]]
 
−
In 2019 TSMC introduced a 2nd-generation N7 process called '''N7 Performance-enhanced''' ('''N7P'''). N7P is an optimized version of TSMC [[#N7|N7]] process. to that end, it remains a [[DUV]]-based process, keeping the same design rules and is fully IP-compatible with N7. N7P introduces [[FEOL]] and [[MOL]] optimizations which are said to translate to either 7% performance improvement at iso-power or up to 10% lower power at iso-speed.
 
−
 
 
−
{| class="wikitable" style="text-align: center;"
 
−
|-
 
−
! colspan="3" | N7 [[PPA]] vs. N7P
 
−
|-
 
−
! Speed @ iso-power !! Power @ iso-speed
 
−
|-
 
−
| ~7% || ~10%
 
−
|}
 
−
 
 
−
For their second generation process, TSMC made some additional optimizations, including fin profile optimizations, [[epitaxial|epi]] optimizations, MOL resistance optimizations, FEOL capacitance reduction, and metal gate optimizations. Additionally, at the same leakage, at high frequencies, the second-generation 7nm process has improved the Vmin by 50 mV.
 
−
 
 
−
{{clear}}
 
−
 
 
−
==== N7+ ====
 
−
The '''N7+ node''' is TSMC's first process technology to adopt [[EUV lithography]]. It is unrelated to both the N7 and N7P processes, and is not IP-compatible with either, requiring re-implementation (new physical layout and validation). N7+ entered mass production in the second quarter of 2019 and uses EUV for four critical layers. Compared to TSMC N7 process, N7+ is said to deliver around 1.2x density improvement. N7+ is also said to deliver 10% higher performance at iso-power or, alternatively, up to 15% lower power at iso-performance. On paper, N7+ appears to be marginally better than N7P, albeit that comes at the cost of re-implementing the design.
 
−
 
 
−
{| class="wikitable" style="text-align: center;"
 
−
|-
 
−
! colspan="3" | N7 [[PPA]] vs. N7+
 
−
|-
 
−
! Speed @ iso-power !! Power @ iso-speed !! Density
 
−
|-
 
−
| ~10% || ~15% || 1.2x
 
 
|}
 
|}
  
−
{{clear}}
+
=== Samsung===
−
 
 
−
=== Samsung ===
 
 
Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development.
 
Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development.
 
On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size.
 
On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size.
−
==== 7LPE ====
 
−
==== 7LPP ====
 
−
=== GlobalFoundries ===
 
−
 
−
* '''Note:'''  As of august 2018 GlobalFoundries has announced they will suspend further development of their 7nm, 5nm and 3nm process.
 
−
[[File:globalfoundries interconnect 7nm.jpg|right|350px]]
 
−
On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of [[EUV]], the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.
 
−
 
−
The 7nm process features SAQP for the FEOL, and double patterning for the BEOL. GlobalFoundries claims a 2.8 times density improvement compared to their 14nm process, and a performance improvement of 40% or a 55% reduction in power consumption. Two versions of the process will be developed: a low power version for mobile applications. And a high performance version for desktop and server chips.
 
−
==== 7LP ====
 
−
==== 7HPC ====
 
  
 
== 7 nm Microprocessors==
 
== 7 nm Microprocessors==
Line 160: Line 215:
 
** {{pezy|PEZY-SC3}}
 
** {{pezy|PEZY-SC3}}
 
* MediaTek
 
* MediaTek
−
** {{mediatek|helio|Helio M70}}
+
** {{mediatek|Helio}}
−
**DImensity 1000
 
−
**Dimensity 800U
 
−
**Dimensity 1000+
 
−
**Dimensity 800
 
−
* Apple
 
−
** {{apple|A12}}
 
−
** {{apple|A12X}}
 
−
** {{apple|A13}}
 
−
* HiSilicon (Huawei)
 
−
** {{hisilicon|kirin|990 4G/5G}}
 
−
** {{hisilicon|kirin|980}}
 
−
** {{hisilicon|kirin|810}}
 
−
* Snapdragon (Qualcomm)
 
−
**Snapdragon 765G
 
−
** {{qualcomm|snapdragon 855|855}}
 
−
** {{qualcomm|snapdragon 865|865}}
 
−
** {{qualcomm|snapdragon 870|870}}
 
−
** {{qualcomm|Snapdragon 865+}}
 
−
* Exynos (Samsung)
 
−
** {{samsung|exynos 990|990}}
 
−
** {{samsung|exynos 9825|9825}}
 
 
{{expand list}}
 
{{expand list}}
  
 
== 7 nm Microarchitectures==
 
== 7 nm Microarchitectures==
 
* AMD
 
* AMD
−
** {{amd|Vega 20|l=arch}}
 
 
** {{amd|Navi|l=arch}}
 
** {{amd|Navi|l=arch}}
 
** {{amd|Zen 2|l=arch}}
 
** {{amd|Zen 2|l=arch}}
Line 201: Line 234:
  
 
== See also ==
 
== See also ==
−
* {{intel|process|Intel process technology history}}
 
  
−
== Bibliography ==
+
* {{intel|process|Intel proces technology history}}
−
* {{bib|iitc|2016|IBM, GlobalFoundries}}
+
 
−
* {{bib|iedm|2016|Samsung}}
+
== References ==
−
* {{bib|isscc|2017|TSMC}}
+
* Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
−
* {{bib|vlsi|2019|Qualcomm, TSMC}}
+
* Standaert, T., et al. "BEOL process integration for the 7 nm technology node." Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. IEEE, 2016.
 +
* Samsung/GlobalFoundries, [[IEEE]] [[International Electron Devices Meeting]] (IEDM) 2016
 +
[[category:lithography]]

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