Editing 500 nm lithography process

{{lithography processes}}
The '''500 nanometer (500 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[600 nm lithography process|600 nm process]]. Commercial [[integrated circuit]] manufacturing using 500 nm process began in 1992. 500 nm and was phased out and later replaced by [[350 nm]] in 1995.

== Industry ==
{{scrolling table/top|style=text-align: right; | first=Fab
 |Process Name
 |1st Production
 |Metal Layers
 |&nbsp;
 |Contacted Gate Pitch
 |Interconnect Pitch (M1P)
 |SRAM bit cell
}}
{{scrolling table/mid}}
|-
! colspan="2" | [[Intel]] || colspan="2" | [[AMD]] || colspan="2" | [[DEC]] || colspan="2" | [[Fujitsu]] || colspan="2" | [[Hitachi]] || colspan="2" | [[HP]] || colspan="2" | [[IBM]] || colspan="2" | [[TI]] || colspan="2" | [[Motorola]] || colspan="2" | [[National Semiconductor|National]] (BiCMOS)
|- style="text-align: center;"
| colspan="2" |P852 || colspan="2" | CS-24 || colspan="2" | CMOS-5 || colspan="2" | || colspan="2" | || colspan="2" | CMOS14C || colspan="2" | CMOS-5X || colspan="2" |  || colspan="2" | HiPerMOS 1 || colspan="2" | ABiC V
|- style="text-align: center;"
| colspan="2" | 1994 || colspan="2" | 1993 || colspan="2" | 1993 || colspan="2" | 1994 || colspan="2" | 1994 || colspan="2" | 1996 || colspan="2" | 1994 || colspan="2" | 1995 || colspan="2" | 1995 || colspan="2" | 
|- style="text-align: center;"
| colspan="2" |  || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 4 || colspan="2" | 4 || colspan="2" |  || colspan="2" | 
|-
! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ !! Value !! [[800 nm]] Δ
|-
| ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
|-
| ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
|-
| 44 µm<sup>2</sup> || 0.40x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
{{scrolling table/end}}

== 500 nm Microprocessors ==
* AMD
** {{amd|Am486}}
** {{amd|K5}} ("SSA/5" models only)
* DEC
** {{decc|Alpha 21164}}
** {{decc|Alpha 21064A}}
** {{decc|Alpha 21164PC}}
* Exponential
** {{expotech|X704}}
* Fujitsu
** {{fujitsu|microSPARC II}} ("Swift")
* Hitachi
** {{hitachi|harp-1}}
* HP
** {{hp|PA-7200}} ("Thunderbird")
** {{hp|PA-7300LC}}
** {{hp|PA-8000}} ("Onyx", "Vulcan")
* IBM
** {{ibm|PowerPC 601v}}
** {{ibm|PowerPC 602}}
** {{ibm|PowerPC 603}}
** {{ibm|PowerPC 603e}}
* Intel
** {{intel|Pentium Pro}}
* NexGen
** {{nexgen|Nx586}}
* Ross
** {{ross|hyperSPARC}} ("Colorado 2")
* Sun
** {{sun|microSPARC II}}, 1994
** {{sun|UltraSPARC}}
{{expand list}}

== 500 nm Microarchitectures ==
{{expand list}}
@@ Line 28: / Line 28: @@
 | ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 |-
-| 44 µm² || 0.40x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x
+| 44 µm<sup>2</sup> || 0.40x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
 {{scrolling table/end}}
-=== DEC ===
-{{see also|dec/process|l1=DEC's Process Technology History}}
-DEC's half-micron process, '''CMOS-5''', which was used for their microprocessors such as the {{decc|Alpha 21164|l=arch}} used a Cabalt di-silicide in diffusion and poly with a channel length of 0.365 µm with a T<sub>OX</sub> of 9 nm along with 4 metal layers of AlCu (Aluminum Copper). The process had a Vtn/p = 0.5/-0.5 V and a supply voltage of 3.3 V.
-{| class="wikitable collapsible collapsed"
-|-
-! colspan="3" | DEC's Design Rules
-|-
-! Layer !! Pitch !! Thickness
-|-
-| M1 || 1.50 µm || 0.84 µm
-|-
-| M2 || 1.75 µm || 0.84 µm
-|-
-| M3 || 5.00 µm || 1.53 µm
-|-
-| M4 || 6.00 µm || 1.53 µm
-|}
 == 500 nm Microprocessors ==
@@ Line 54: / Line 35: @@
 ** {{amd|Am486}}
 ** {{amd|K5}} ("SSA/5" models only)
-* Cyrix
-** {{cyrix|6x86}}
 * DEC
 ** {{decc|Alpha 21164}}
@@ Line 79: / Line 58: @@
 * NexGen
 ** {{nexgen|Nx586}}
-* Qualcomm
-** {{qualcomm|MSM2}}
 * Ross
 ** {{ross|hyperSPARC}} ("Colorado 2")
@@ Line 89: / Line 66: @@
 == 500 nm Microarchitectures ==
-* AMD
-** {{amd|K5|l=arch}}
-* DEC
-** {{decc|Alpha 21164|l=arch}}
-* Intel
-** {{intel|80186|l=arch}} (embedded [[IP cores]] only)
 {{expand list}}
-[[category:lithography]]