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Editing 45 nm lithography process
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== Industry == | == Industry == | ||
− | In January of 2006 Intel announced that they've been able to fabricate the first fully functional [[SRAM]] chips on a 45 nm process. As a preview Intel showcased 45nm SRAM chip (shown below) packing more than 1 billion transistors. Intel opened 3 45 nm facilities, their initial {{intel|D1D}} facility in Oregon, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel | + | In January of 2006 Intel announced that they've been able to fabricate the first fully functional [[SRAM]] chips on a 45 nm process. As a preview Intel showcased 45nm SRAM chip (shown below) packing more than 1 billion transistors. Intel opened 3 45 nm facilities, their initial {{intel|D1D}} facility in Oregon, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel. |
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
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! colspan="2" | [[Intel]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[TI]] !! colspan="2" | [[Toshiba]] / [[Sony]] / [[NEC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] | ! colspan="2" | [[Intel]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[TI]] !! colspan="2" | [[Toshiba]] / [[Sony]] / [[NEC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | P1266 | + | | colspan="2" | P1266 || colspan="2" | CS-300 || colspan="2" | || colspan="2" | || colspan="2" | 11LP || colspan="2" | |
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | 2006 || colspan="2" | 2008 || colspan="2" | 2008 || colspan="2" | 2006 || colspan="2" | 2007 || colspan="2" | 2007 | | colspan="2" | 2006 || colspan="2" | 2008 || colspan="2" | 2008 || colspan="2" | 2006 || colspan="2" | 2007 || colspan="2" | 2007 | ||
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| 0.346 µm² || 0.61x || 0.225 µm² || ?x || 0.255 µm² || ?x || 0.248 µm² || ?x || 0.29 µm² || 0.54x || 0.370 µm² || 0.57x | | 0.346 µm² || 0.61x || 0.225 µm² || ?x || 0.255 µm² || ?x || 0.248 µm² || ?x || 0.29 µm² || 0.54x || 0.370 µm² || 0.57x | ||
|- | |- | ||
− | | 0. | + | | 0.382 µm² || 0.56x || || || || || || || 0.359 µm² || 0.53x || || |
|- | |- | ||
| || || || || || || || || 0.11 µm² || 0.58x || 0.067 µm² || 0.53x | | || || || || || || || || 0.11 µm² || 0.58x || 0.067 µm² || 0.53x | ||
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** {{amd|Opteron}} | ** {{amd|Opteron}} | ||
** {{amd|Phenom II}} | ** {{amd|Phenom II}} | ||
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* IBM | * IBM | ||
** {{ibm|Power7}} | ** {{ibm|Power7}} | ||
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== 45 nm Microarchitectures == | == 45 nm Microarchitectures == | ||
+ | * Intel | ||
+ | ** {{intel|microarchitectures/bonnell|Bonnell}} | ||
+ | ** {{intel|microarchitectures/nehalem|Nehalem}} | ||
+ | ** {{intel|microarchitectures/penryn|Penryn}} | ||
* AMD | * AMD | ||
− | ** {{amd|K10 | + | ** {{amd|microarchitectures/k10|K10}} |
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{{expand list}} | {{expand list}} | ||
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