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{{lithography processes}} | {{lithography processes}} | ||
− | The '''14 nanometer (14 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[22 nm process]]. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and | + | The '''14 nanometer (14 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[22 nm process]]. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and is currently getting replaced by the [[10 nm process]]. |
== Industry == | == Industry == | ||
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| process 1 dram Δ = | | process 1 dram Δ = | ||
<!-- Samsung --> | <!-- Samsung --> | ||
− | | process 2 fab = [[Samsung]]<info>'''Samsung''' consists of a process development collaboration between [[Samsung]] and [[GlobalFoundries]]. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York.</info> | + | | process 2 fab = [[Samsung]] Alliance<info>'''Samsung Alliance''' consists of a process development collaboration between [[Samsung]] and [[GlobalFoundries]]. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York.</info> |
| process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | | process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | ||
| process 2 date = 2015 | | process 2 date = 2015 | ||
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| process 5 dram Δ = | | process 5 dram Δ = | ||
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This process became Samsung's and GlobalFoundries first generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Samsung node has gone through a number of refinements from 14LPE (14 Low-Power Early) to 14LPP (14 Low-Power Performance) and further. | This process became Samsung's and GlobalFoundries first generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Samsung node has gone through a number of refinements from 14LPE (14 Low-Power Early) to 14LPP (14 Low-Power Performance) and further. | ||
=== 11LPP === | === 11LPP === | ||
− | In late 2017, Samsung announced "11LPP" (11 Low-Power Plus) which is a further enhancement of 14LPP. 11LPP is reported to deliver up to 15% higher performance with enhanced design rules that allow for up to 10% reduction in area. Samsung expects 11LPP to enter mass production in late 2017 or early 2018 | + | In late 2017, Samsung announced "11LPP" (11 Low-Power Plus) which is a further enhancement of 14LPP. 11LPP is reported to deliver up to 15% higher performance with enhanced design rules that allow for up to 10% reduction in area. Samsung expects 11LPP to enter mass production in late 2017 or early 2018. |
=== GlobalFoundries === | === GlobalFoundries === | ||
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** {{intel|Cascade Lake|l=arch}} | ** {{intel|Cascade Lake|l=arch}} | ||
** {{intel|Cooper Lake|l=arch}} | ** {{intel|Cooper Lake|l=arch}} | ||
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* AMD | * AMD | ||
** {{amd|Zen|l=arch}} | ** {{amd|Zen|l=arch}} |