Editing 14 nm lithography process

{{lithography processes}}
The '''14 nanometer (14 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[22 nm process]]. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and is currently getting replaced by the [[10 nm process]].

== Industry ==

{{finfet nodes comp
<!-- Intel -->
 | process 1 fab          = [[Intel]]
 | process 1 name         = P1272 (CPU) / P1273 (SoC)
 | process 1 date         = 2014
 | process 1 lith         = 193 nm
 | process 1 immersion    = Yes
 | process 1 exposure     = SADP
 | process 1 wafer type   = Bulk
 | process 1 wafer size   = 300 mm
 | process 1 transistor   = FinFET
 | process 1 volt         = 0.70 V
 | process 1 delta from   = [[22 nm]] Δ
 | process 1 fin pitch    = 42 nm
 | process 1 fin pitch Δ  = 0.70x
 | process 1 fin width    = 8 nm
 | process 1 fin width Δ  = 1.00x
 | process 1 fin height   = 42 nm
 | process 1 fin height Δ = 1.24x
 | process 1 gate len     = 20 nm
 | process 1 gate len Δ   = 0.77x
 | process 1 cpp          = 70 nm
 | process 1 cpp Δ        = 0.78x
 | process 1 mmp          = 52 nm
 | process 1 mmp Δ        = 0.65x
 | process 1 sram hp      = 0.0706 µm²
 | process 1 sram hp Δ    = 0.54x
 | process 1 sram hd      = 0.0499 µm²
 | process 1 sram hd Δ    = 0.54x
 | process 1 sram lv      = 0.0588 µm²
 | process 1 sram lv Δ    = 0.54x
 | process 1 dram         = &nbsp;
 | process 1 dram Δ       = &nbsp;
<!-- Samsung -->
 | process 2 fab          = [[Samsung]] Alliance<info>'''Samsung Alliance''' consists of a process development collaboration between [[Samsung]] and [[GlobalFoundries]]. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York.</info>
 | process 2 name         = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info>
 | process 2 date         = 2015
 | process 2 lith         = 193 nm
 | process 2 immersion    = Yes
 | process 2 exposure     = LELE
 | process 2 wafer type   = Bulk
 | process 2 wafer size   = 300 mm
 | process 2 transistor   = FinFET
 | process 2 volt         = 0.80 V
 | process 2 delta from   = [[20 nm]] Δ
 | process 2 fin pitch    = 48 nm
 | process 2 fin pitch Δ  = -
 | process 2 fin width    = 8 nm
 | process 2 fin width Δ  = &nbsp;
 | process 2 fin height   = ~38 nm
 | process 2 fin height Δ = &nbsp;
 | process 2 gate len     = 30 nm
 | process 2 gate len Δ   = &nbsp;
 | process 2 cpp          = 78 nm
 | process 2 cpp Δ        = 1.22x
 | process 2 mmp          = 64 nm
 | process 2 mmp Δ        = 1.00x
 | process 2 sram hp      = 0.080 µm²
 | process 2 sram hp Δ    = 0.78x
 | process 2 sram hd      = 0.064 µm²
 | process 2 sram hd Δ    = 0.79x
 | process 2 sram lv      = &nbsp;
 | process 2 sram lv Δ    = &nbsp;
 | process 2 dram         = &nbsp;
 | process 2 dram Δ       = &nbsp;
<!-- IBM -->
 | process 3 fab          = [[IBM]]
 | process 3 name         = 14HP<info>14nm High Performance</info>
 | process 3 date         = 2017
 | process 3 lith         = 193 nm
 | process 3 immersion    = Yes
 | process 3 exposure     = SADP
 | process 3 wafer type   = SOI
 | process 3 wafer size   = 300 mm
 | process 3 transistor   = FinFET
 | process 3 volt         = 0.80 V
 | process 3 delta from   = [[22 nm]] Δ
 | process 3 fin pitch    = 42 nm
 | process 3 fin pitch Δ  = -
 | process 3 fin width    = 10 nm
 | process 3 fin width Δ  = &nbsp;
 | process 3 fin height   = 25 nm
 | process 3 fin height Δ = &nbsp;
 | process 3 gate len     = 18-26 nm
 | process 3 gate len Δ   = 0.72-0.79x
 | process 3 cpp          = 80 nm
 | process 3 cpp Δ        = 0.80x
 | process 3 mmp          = 64 nm
 | process 3 mmp Δ        = 0.80x
 | process 3 sram hp      = 0.0900 µm²
 | process 3 sram hp Δ    = 0.63x
 | process 3 sram hd      = 0.0810 µm²
 | process 3 sram hd Δ    = 0.81x
 | process 3 sram lv      = &nbsp;
 | process 3 sram lv Δ    = &nbsp;
 | process 3 dram         = 0.0174 µm²
 | process 3 dram Δ       = 0.67x
<!-- UMC -->
 | process 4 fab          = [[UMC]]
 | process 4 name         = &nbsp;
 | process 4 date         = &nbsp;
 | process 4 lith         = 193 nm
 | process 4 immersion    = &nbsp;
 | process 4 exposure     = &nbsp;
 | process 4 wafer type   = &nbsp;
 | process 4 wafer size   = 300 mm
 | process 4 transistor   = FinFET
 | process 4 volt         = &nbsp;
 | process 4 delta from   = [[28 nm]] Δ
 | process 4 fin pitch    = &nbsp;
 | process 4 fin pitch Δ  = &nbsp;
 | process 4 fin width    = &nbsp;
 | process 4 fin width Δ  = &nbsp;
 | process 4 fin height   = &nbsp;
 | process 4 fin height Δ = &nbsp;
 | process 4 gate len     = &nbsp;
 | process 4 gate len Δ   = &nbsp;
 | process 4 cpp          = &nbsp;
 | process 4 cpp Δ        = &nbsp;
 | process 4 mmp          = &nbsp;
 | process 4 mmp Δ        = &nbsp;
 | process 4 sram hp      = &nbsp;
 | process 4 sram hp Δ    = &nbsp;
 | process 4 sram hd      = &nbsp;
 | process 4 sram hd Δ    = &nbsp;
 | process 4 sram lv      = &nbsp;
 | process 4 sram lv Δ    = &nbsp;
 | process 4 dram         = &nbsp;
 | process 4 dram Δ       = &nbsp;
<!-- UMC -->
 | process 5 fab          = [[Common Platform Alliance]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[STMicroelectronics]]</info>
 | process 5 name         = 14FDSOI
 | process 5 date         = &nbsp;
 | process 5 lith         = 193 nm
 | process 5 immersion    = Yes
 | process 5 exposure     = DP
 | process 5 wafer type   = SOI
 | process 5 wafer size   = 300 mm
 | process 5 transistor   = Planar
 | process 5 volt         = 0.80 V
 | process 5 delta from   = [[28 nm]] Δ
 | process 5 fin pitch    = -
 | process 5 fin pitch Δ  = &nbsp;
 | process 5 fin width    = &nbsp;
 | process 5 fin width Δ  = &nbsp;
 | process 5 fin height   = &nbsp;
 | process 5 fin height Δ = &nbsp;
 | process 5 gate len     = 20 nm
 | process 5 gate len Δ   = 0.71x
 | process 5 cpp          = 90 nm
 | process 5 cpp Δ        = 0.79x
 | process 5 mmp          = 64 nm
 | process 5 mmp Δ        = 0.71x
 | process 5 sram hp      = 0.090 µm²
 | process 5 sram hp Δ    = 0.59x
 | process 5 sram hd      = 0.081 µm²
 | process 5 sram hd Δ    = 0.68x
 | process 5 sram lv      = &nbsp;
 | process 5 sram lv Δ    = &nbsp;
 | process 5 dram         = &nbsp;
 | process 5 dram Δ       = &nbsp;
}}

=== Composition ===
[[File:intel 14nm relative density.png|left|200px]][[File:relative percentage of elements on 14nm chip.png|right|400px]]
It's important tot note that not all processes compete with each other. The process should cater to the products that will make use of the underlying technology. The composition of the actual integrated circuit also varies by manufacturer and by design due to different goals. For example, the cache on [[Apple]]'s 14 nm {{apple|A9}} (manufactured by Samsung) accounts almost 1/3 of the entire chip whereas [[Intel]]'s {{intel|Broadwell|l=arch}} cache accounts for only 10% of the entire chip. Likewise, [[Intel]]'s {{intel|Broadwell|l=arch}} and {{intel|Skylake|l=arch}} target high-performance and incorporate a large amount of higher-speed elements which are inherently sparse. Tall cells account for almost 30% Skylake's composition and less than 1% on Apple's {{apple|A8}} or {{apple|A9}}. 

It should be noted that [[SRAM]] is the least dense component of the process in a chip, with sometimes up to three or four times less than the density of logic cells that are used in the same process. In recent years, SRAM hasn't scaled as well as logic and I/O have either.

=== Intel ===
{{see also|intel/process|l1=Intel's Process Technology History}}
Intel got off to a bumpy start with major yield problems initially, but by {{intel|Skylake|l=arch}} yield has reached very healthy numbers. 14 nm became [[Intel]]'s 2nd generation FinFET transistors. Intel uses TiN pMOS / TiAlN nMOS as work function metals. Intel makes use of 193 nm immersion lithography with [[Self-Aligned Double Patterning]] (SADP) at the critical patterning layers. Compared to all other "14 nm nodes", Intel's process is the densest and considerably so, with >1.5x raw logic density.

Intel's 14 nm process has gone through multiple refinements optimizing higher clock speed, higher drive current, and lower power dissipation. The original "14nm" was used for their {{intel|Broadwell|l=arch}} and mainstream {{intel|Skylake|l=arch}} processors. They improved on their original process with a second process, "14nm+", offering 12% higher drive current at lower power. That process has been used for both {{intel|Kaby Lake|l=arch}} and Server/HEDT {{intel|Skylake SP|l=core}}/{{intel|Skylake X|X|l=core}} processors.

A third improved process, "14nm++", is set to begin in late 2017 and will further allow for +23-24% higher drive current for 52% less power vs the original 14nm process. The 14nm++ process also appear to have slightly relaxed poly pitch of 84 nm (from 70 nm). It's unknown what impact, if any, this will have on the density.

[[File:intel 14nm gate.png|250px]]
{| class="wikitable collapsible collapsed"
|-
! colspan="3" | Intel 14nm Design Rules
|-
! Layer !! Pitch !! Scale Factor
|-
| Fin || 42 nm || 0.70
|-
| Contacted Gate Pitch || 70 nm || 0.78
|-
| Metal 0 || 56 || -
|-
| Metal 1 || 70 || 0.78
|-
| Metal 2 || 52 || 0.65
|}

=== IBM ===
[[File:ibm 14nm m1 cx.png|right|300px]]
[[File:ibm 14nm m2 cx.png|right|300px]]
IBM developed their own "14HP" (14nm High-Performance) process at their East Fishkill, NY plant. Note that the plant AND the process, along with numerous semiconductor technology IPs, were sold to [[GlobalFoundries]] in late 2014. GF still operates the plant (also by ex-IBM semicondcutor engineers) and the process which is used by IBM for their various processors. This process was designed by IBM for their very large chips with effective power supply and clock distribution capable of producing dies as large as 700 mm² and larger with a hierarchical [[BEOL]] of 17 levels of copper interconnect for high performance wire-ability. It should be noted that GlobalFoundries had no such capabilities prior to their acquisition of IBM's plant, semiconductor manufacturing group, and IP portfolio.

IBM's HP 14nm CMOS process features a [[FinFET]] architecture on an [[silicon-on-insulator|SOI]] substrate. The use of SOI with [[FinFet]] gives IBM a number of unique advantages such as lower [[parasitic capacitance]] at the base of the fin as well as simplifies patterning of the active fins and minimizes their variability such as height and thickness. The architecture also includes high-density deep-trench [[embedded DRAM]] cells with a reported size of 0.0174 µm². The process features an L<sub>gate</sub> of 20nm and smaller (18nm to 27nm) which IBM reported to result in over 35% performance gain verses their HP 22nm process (for identical V<sub>dd</sub> = 0.80 V).


{| class="wikitable collapsible collapsed"
|-
! colspan="3" | IBM 14nm Design Rules
|-
! Layer !! Pitch
|-
| Fin || 42 nm
|-
| Contacted Gate Pitch || 80 nm
|-
| Metal 1 || 64 nm
|-
| Metal 2 || 80 nm
|-
| Metal 3 || 128 nm
|-
| Metal 4 || 256 nm
|-
| Metal 5 || 512 nm
|-
| Metal 6 || 2.56 µm
|}

=== Samsung ===
This process became Samsungs' and GlobalFoundries first generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals.

== Find models ==
{{#ask: [[instance of::microprocessor]] [[process::14 nm]]
 |?microprocessor family
 |?microarchitecture
 |?process
 |?designer
 |?manufacturer
 |?first launched
 |?base frequency
 |format=broadtable
 |link=all
 |headers=show
 |limit=0
 |searchlabel=Click to browse all 14 nm MPU models
 |class=sortable wikitable smwtable
}}

== 14 nm Microprocessors==
* Intel
{{collist
| count = 6
| style = padding-left: 30px
|
* {{intel|Atom x5}}
* {{intel|Atom x7}}
* {{intel|Core i3}}
* {{intel|Core i5}}
* {{intel|Core i7}}
* {{intel|Core i7EE}}
* {{intel|pentium (2009)|Pentium}}
* {{intel|Celeron}}
* {{intel|Xeon}}
* {{intel|Xeon Bronze}}
* {{intel|Xeon D}}
* {{intel|Xeon E3}}
* {{intel|Xeon E5}}
* {{intel|Xeon E7}}
* {{intel|Xeon Gold}}
* {{intel|Xeon Platinum}}
* {{intel|Xeon Silver}}
}}
* AMD
{{collist
| count = 4
| style = padding-left: 30px
|
* {{amd|EPYC}}
* {{amd|Ryzen 3}}
* {{amd|Ryzen 5}}
* {{amd|Ryzen 7}}
}}
* Samsung
** {{samsung|Exynos}}
* NXP
** {{nxp|i.MX 8M Mini}}

{{expand list}}

== 14 nm Microarchitectures==
* Intel
** {{intel|Airmont|l=arch}}
** {{intel|Goldmont|l=arch}}
** {{intel|Broadwell|l=arch}}
** {{intel|Skylake|l=arch}}
** {{intel|Kaby Lake|l=arch}}
** {{intel|Coffee Lake|l=arch}}
* AMD
** {{amd|Zen|l=arch}}
* IBM
** {{ibm|POWER9|l=arch}}
** {{ibm|z14|l=arch}}

{{expand list}}

== Documents ==
* [[:File:14-nm-technology-fact-sheet.pdf|Intel's 14 nm Technology: Delivering Ultrafast, Energy-Sipping Products]]
* [[:File:2015 InvestorMeeting Bill Holt WEB2.pdf|Intel's 14nm, Advancing Moore's Law, investor meeting]]

== References ==
* Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
* Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
* Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015.
* Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169.
* Weber, Olivier, et al. "14nm FDSOI technology for high speed and energy efficient applications." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.
* Chen, Shyng-Tsong, et al. "64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme." Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International. IEEE, 2011.

[[Category:Lithography]]