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Alchemy Au1550-333MBC
General Info
Designer	AMD
Model Number	Au1550-333MBC
Part Number	Au1550-333MBCAA
Market	Embedded
Introduction	February 24, 2004 (announced) May 2004 (launched)
Release Price	$21.26 (tray)
Shop	Amazon
General Specs
Family	Alchemy
Frequency	333 MHz
Microarchitecture
ISA	MIPS32
Microarchitecture	Au1
Core Stepping	AA
Technology	CMOS
Word Size	32 bit
Cores	1
Max Memory	192 MiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.2 V ± 10%
VI/O	3.3 V
TDP	1350 mW
TDP (Typical)	400 mW
Tcase	0 °C – 85 °C
Tstorage	-40 °C – 125 °C

Au1550-333MBC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by AMD based on earlier Alchemy Semiconductor processors this SoC operates at a base frequency of up to 333 MHz with a typical TDP of 400 mW and maximum TDP of 1350 mW. It was also available with an industrial temperature range as Au1550-333MBI and a Pb-free version Au1550-333MBD.

Cache

Main article: Au1 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 32 KiB 32,768 B 0.0313 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative write-back

Memory controller

Au1550 processors integrate two independent memory controllers, an SDRAM controller which supports 3.3 V and 2.5 V SDR devices and 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, and I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type SDR-166, DDR-400 Supports ECC No Max Mem 192 MiB Controllers 1 Channels 1 Width 16 bit, 32 bit Max Bandwidth 1.332 GB/s 1.241 GiB/s 1,270.294 MiB/s 1,332 MB/s 0.00121 TiB/s 0.00133 TB/s

Expansions

• PCI 2.2 controller, 32-bit bus, 33 or 66 MHz
• USB 1.1 (OHCI) host controller, USB 1.1 device controller with OTG support
  • Two USB host ports and one device port (co-opting a host port in OTG mode)
• Two 10/100 Mbit/s Ethernet MAC controllers
• Four Programmable Serial Controllers supporting the AC97, I2S, SPI, and SMBus protocols
• Three UARTs
• Up to 43 GPIOs

Graphics

This processor has no integrated graphics processing unit.

Features

• 16-channel descriptor-based DMA controller
  • Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
  • 36-bit source and destination addresses with no alignment requirement
  • Scatter/gather and stride transfers
  • Compare and branch descriptors
• SafeNet Security Engine to accelerate IP packet encryption/decryption in hardware
  • DES, 3DES, AES, ARC4 encryption algorithms
  • MD5, SHA1 hash algorithms
  • Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets
  • Supports a two-pass hash-then-encrypt implementation of the SSL protocol using either MD5 or SHA1 and 3DES or ARC4 ciphers
  • True entropy-based random number generator
• RTC and TOY timer
• Two interrupt controllers
• Power management unit
• MIPS EJTAG interface
• Idle, Sleep, Hibernate Mode

Package

• 483-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
• 25 × 25 grid, 0.8 mm pitch
• 21 mm × 21 mm × 1.7 mm

Bibliography

• "Product Brief: AMD Alchemy™ Au1550™ Processor Security Network Processor", AMD Publ. #31195, Rev. C, 2004
• "AMD Alchemy™ Au1550™ Security Network Processor Data Book", AMD Publ. #30283, Rev. D, May 2006