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- |isa=x86-64 * New memory model for {{x86|TSX|Transactional Synchronization Extensions}}27 KB (3,750 words) - 06:57, 18 November 2023
- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]79 KB (11,922 words) - 06:46, 11 November 2022
- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]30 KB (4,192 words) - 13:48, 10 December 2023
- |isa=x86-64 **** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.15 KB (1,978 words) - 22:13, 6 April 2023
- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{x86|AVX-512}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]52 KB (7,651 words) - 00:59, 6 July 2022
- |isa=x86-64 ...'''), the successor to {{\\|Palm Cove}}, is a high-performance [[10 nm]] [[x86]]-64 core microarchitecture designed by [[Intel]] for an array of server an34 KB (5,187 words) - 06:27, 17 February 2023
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