Edit Values | |
Alchemy Au1250-400MGF | |
General Info | |
Designer | RMI |
Model Number | Au1250-400MGF |
Part Number | Au1250-400MGF |
Market | Embedded |
Introduction | January 9, 2007 (announced) June 5, 2007 (launched) |
General Specs | |
Family | Alchemy |
Frequency | 400 MHz |
Microarchitecture | |
ISA | MIPS32 |
Microarchitecture | Au1 |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Max Memory | 512 MiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.2 V ± 10% |
VI/O | 3.3 V |
TDP | 1200 mW |
TDP (Typical) | 560 mW |
Tcase | -40 °C – 100 °C |
Tstorage | -40 °C – 125 °C |
Au1250-400MGF was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by RMI based on earlier AMD and Alchemy Semiconductor processors this SoC operates at a base frequency of up to 400 MHz with a typical TDP of 560 mW and maximum TDP of 1200 mW. It has an industrial temperature range of -40 to 100 °C unlike its commercial counterpart Au1250-400MGD.
Cache
- Main article: Au1 § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||
|
Memory controller
Au1250 processors integrate two independent memory controllers, a DRAM controller which supports 2.5 V DDR and 1.8 V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, IDE PIO mode, and other I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency. The integrated LCD and MAE peripherals can access the SDRAM controller through a 64-bit side bus running at the SBUS frequency.
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
- USB 2.0 (EHCI) and 1.1 (OHCI) host controller, USB 2.0 device controller with OTG support
- One USB host port and one host/device port, each low/fast/high speed capable
- Two Secure Digital/SDHC/SDIO/MMC 1.1 controllers
- Two Programmable Serial Controllers supporting the AC97, I2S, SPI, and SMBus protocols
- Two UARTs
- Up to 48 GPIOs
Graphics
This processor integrates an LCD controller for panels with a resolution up to 2048 × 2048 pixels.
- TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
- STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
- Frame buffer formats:
- 1/2/4/8-bpp pass through/grayscale/palettized
- 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1, 4:4:4:0
- 24-bpp 8:8:8:0
- 32-bpp 8:8:8:8 RGBA
- Four overlay windows with double buffering
- Gamma correction, alpha blending, and chroma keying
- 32 × 32 × 2 bpp hardware cursor
Features
- Camera Interface Module (CIM)
- ITU-R BT.656 compatible 8/9/10-bit bus running at up to 33 MHz
- Support for UYVY and Bayer RGB to planar format conversion
- Media Acceleration Engine (MAE) to accelerate video decoding in hardware
- Formats MPEG-1/2/4, DivX-3/4/5, H.263, WMV9, VC-1
- Accelerates inverse quantization, inverse DCT, motion compensation, WMV9 filters
- Hardware colorspace conversion and scaling with 4-tap filter, also for CIM
- Video decode resolution up to D1 720 × 480 NTSC / 720 × 576 PAL
- 16-channel descriptor-based DMA controller
- Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
- 36-bit source and destination addresses with no alignment requirement
- Scatter/gather and stride transfers
- Compare and branch descriptors
- AES-128 encryption/decryption in hardware with ECB, CBC, CFB, and OFB block cipher modes
- RTC and TOY timer
- Two interrupt controllers
- Power management unit
- MIPS EJTAG interface
- Idle, Sleep, Hibernate Mode
Package
- 372-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
- 23 × 23 grid, 0.8 mm pitch
- 19 mm × 19 mm × 1.4 mm
Bibliography
- "RMI Alchemy™ Au1210™ Navigation Processor and Au1250™ Media Processor Data Book", RMI Corp., Rev. A, April 2007
base frequency | 400 MHz (0.4 GHz, 400,000 kHz) + |
core count | 1 + |
core voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
core voltage tolerance | 10% + |
designer | RMI + |
family | Alchemy + |
first announced | January 9, 2007 + |
first launched | June 5, 2007 + |
full page name | alchemy/au1250-400mgf + |
has ecc memory support | false + |
has feature | industrial temperature range + |
instance of | microprocessor + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | MIPS32 + |
l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
ldate | June 5, 2007 + |
market segment | Embedded + |
max case temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max cpu count | 1 + |
max memory | 512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB, 4.882812e-4 TiB) + |
max memory bandwidth | 1.49 GiB/s (1,525.879 MiB/s, 1.6 GB/s, 1,600 MB/s, 0.00146 TiB/s, 0.0016 TB/s) + |
max memory channels | 1 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Au1 + |
min case temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | Au1250-400MGF + |
name | Alchemy Au1250-400MGF + |
part number | Au1250-400MGF + |
smp max ways | 1 + |
supported memory type | DDR-400 + and DDR2-533 + |
tdp | 1.2 W (1,200 mW, 0.00161 hp, 0.0012 kW) + |
tdp (typical) | 0.56 W (560 mW, 7.5096e-4 hp, 5.6e-4 kW) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |