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Alchemy Au1200-500MGC
General Info
Designer	AMD
Model Number	Au1200-500MGC
Part Number	Au1200-500MGC
Market	Embedded
Introduction	January 3, 2005 (announced) May 2005 (launched)
Shop	Amazon
General Specs
Family	Alchemy
Frequency	500 MHz
Microarchitecture
ISA	MIPS32
Microarchitecture	Au1
Technology	CMOS
Word Size	32 bit
Cores	1
Max Memory	512 MiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.2 V ± 10%
VI/O	3.3 V
TDP	1600 mW
Tcase	0 °C – 70 °C
Tstorage	-40 °C – 125 °C

Au1200-500MGC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by AMD based on earlier Alchemy Semiconductor processors this SoC operates at a base frequency of up to 500 MHz with a maximum TDP of 1600 mW. It was also available as a Pb-free version Au1200-500MGD.

Cache

Main article: Au1 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 32 KiB 32,768 B 0.0313 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative write-back

Memory controller

Au1200 processors integrate two independent memory controllers, a DRAM controller which supports 2.5 V DDR and 1.8 V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, IDE PIO mode, and other I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency. The integrated LCD and MAE peripherals can access the SDRAM controller through a 64-bit side bus running at the SBUS frequency.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR-400, DDR2-533 Supports ECC No Max Mem 512 MiB Controllers 1 Channels 1 Width 16 bit, 32 bit Max Bandwidth 2 GB/s 1.863 GiB/s 1,907.349 MiB/s 2,000 MB/s 0.00182 TiB/s 0.002 TB/s

Expansions

• USB 2.0 (EHCI) and 1.1 (OHCI) host controller, USB 2.0 device controller with OTG support
  • One USB host port and one host/device port, each low/fast/high speed capable
• Two Secure Digital/SDHC/SDIO/MMC 1.1 controllers
• Two Programmable Serial Controllers supporting the AC97, I2S, SPI, and SMBus protocols
• Two UARTs
• Up to 48 GPIOs

Graphics

This processor integrates an LCD controller for panels with a resolution up to 2048 × 2048 pixels.

• TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
• STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
• Frame buffer formats:
  • 1/2/4/8-bpp pass through/grayscale/palettized
  • 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1, 4:4:4:0
  • 24-bpp 8:8:8:0
  • 32-bpp 8:8:8:8 RGBA
• Four overlay windows with double buffering
• Gamma correction, alpha blending, and chroma keying
• 32 × 32 × 2 bpp hardware cursor

Features

• Camera Interface Module (CIM)
  • ITU-R BT.656 compatible 8/9/10-bit bus running at up to 33 MHz
  • Support for UYVY and Bayer RGB to planar format conversion
• Media Acceleration Engine (MAE) to accelerate video decoding in hardware
  • Formats MPEG-1/2/4, DivX-3/4/5, H.263, WMV9, VC-1
  • Accelerates inverse quantization, inverse DCT, motion compensation, WMV9 filters
  • Hardware colorspace conversion and scaling with 4-tap filter, also for CIM
  • Video decode resolution up to D1 720 × 480 NTSC / 720 × 576 PAL
• 16-channel descriptor-based DMA controller
  • Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
  • 36-bit source and destination addresses with no alignment requirement
  • Scatter/gather and stride transfers
  • Compare and branch descriptors
• AES-128 encryption/decryption in hardware with ECB, CBC, CFB, and OFB block cipher modes
• RTC and TOY timer
• Two interrupt controllers
• Power management unit
• MIPS EJTAG interface
• Idle, Sleep, Hibernate Mode

Package

• 372-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
• 23 × 23 grid, 0.8 mm pitch
• 19 mm × 19 mm × 1.4 mm

Bibliography

• "Product Brief: AMD Alchemy™ Au1200™ Processor", AMD Publ. #32694, Rev. A, 2004
• "AMD Alchemy™ Au1200™ Processor Data Book", AMD Publ. #32798, Rev. E, February 2006
• Eno, Jim. "White Paper: AMD Alchemy™ Au1200™ Processor System Architecture", AMD Publ. #32785, Rev. A, 2005
• Schlanger, Erik. "White Paper: AMD Alchemy™ Au1200™ Processor Media Acceleration Engine", AMD Publ. #32786, Rev. B, January 5, 2005
• Harton, Tracy; Kuczynski, Craig. "White Paper: AMD Alchemy™ Au1200™ Processor LCD Controller", AMD Publ. #32787, Rev. A, 2005
• Lienenbrugger, Kevin. "White Paper: AMD Alchemy™ Au1200™ Camera Interface Module", AMD Publ. #32788, Rev. A, 2005