Edit Values | |
Alchemy Au1550-333MBD | |
General Info | |
Designer | AMD |
Model Number | Au1550-333MBD |
Part Number | Au1550-333MBDAA |
Market | Embedded |
Introduction | February 24, 2004 (announced) May 2004 (launched) |
Release Price | $21.26 (tray) |
Shop | Amazon |
General Specs | |
Family | Alchemy |
Frequency | 333 MHz |
Microarchitecture | |
ISA | MIPS32 |
Microarchitecture | Au1 |
Core Stepping | AA |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Max Memory | 192 MiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.2 V ± 10% |
VI/O | 3.3 V |
TDP | 1350 mW |
TDP (Typical) | 400 mW |
Tcase | 0 °C – 85 °C |
Tstorage | -40 °C – 125 °C |
Au1550-333MBD was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by AMD based on earlier Alchemy Semiconductor processors this SoC operates at a base frequency of up to 333 MHz with a typical TDP of 400 mW and maximum TDP of 1350 mW. It was also available with an industrial temperature range as Au1550-333MBF and is the Pb-free version of the Au1550-333MBC.
Cache
- Main article: Au1 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Au1550 processors integrate two independent memory controllers, an SDRAM controller which supports 3.3 V and 2.5 V SDR devices and 2.5 V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, and I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency.
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Integrated Memory Controller
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Expansions
- PCI 2.2 controller, 32-bit bus, 33 or 66 MHz
- USB 1.1 (OHCI) host controller, USB 1.1 device controller with OTG support
- Two USB host ports and one device port (co-opting a host port in OTG mode)
- Two 10/100 Mbit/s Ethernet MAC controllers
- Four Programmable Serial Controllers supporting the AC97, I2S, SPI, and SMBus protocols
- Three UARTs
- Up to 43 GPIOs
Graphics
This processor has no integrated graphics processing unit.
Features
- 16-channel descriptor-based DMA controller
- Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
- 36-bit source and destination addresses with no alignment requirement
- Scatter/gather and stride transfers
- Compare and branch descriptors
- SafeNet Security Engine to accelerate IP packet encryption/decryption in hardware
- DES, 3DES, AES, ARC4 encryption algorithms
- MD5, SHA1 hash algorithms
- Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets
- Supports a two-pass hash-then-encrypt implementation of the SSL protocol using either MD5 or SHA1 and 3DES or ARC4 ciphers
- True entropy-based random number generator
- RTC and TOY timer
- Two interrupt controllers
- Power management unit
- MIPS EJTAG interface
- Idle, Sleep, Hibernate Mode
Package
- 483-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
- 25 × 25 grid, 0.8 mm pitch
- 21 mm × 21 mm × 1.7 mm
Bibliography
- "Product Brief: AMD Alchemy™ Au1550™ Processor Security Network Processor", AMD Publ. #31195, Rev. C, 2004
- "AMD Alchemy™ Au1550™ Security Network Processor Data Book", AMD Publ. #30283, Rev. D, May 2006
base frequency | 333 MHz (0.333 GHz, 333,000 kHz) + |
core count | 1 + |
core stepping | AA + |
core voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
core voltage tolerance | 10% + |
designer | AMD + |
family | Alchemy + |
first announced | February 24, 2004 + |
first launched | May 2004 + |
full page name | alchemy/au1550-333mbd + |
has ecc memory support | false + |
instance of | microprocessor + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | MIPS32 + |
l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
ldate | May 2004 + |
market segment | Embedded + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 1 + |
max memory | 192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) + |
max memory bandwidth | 1.241 GiB/s (1,270.294 MiB/s, 1.332 GB/s, 1,332 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
max memory channels | 1 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Au1 + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | Au1550-333MBD + |
name | Alchemy Au1550-333MBD + |
part number | Au1550-333MBDAA + |
release price | $ 21.26 (€ 19.13, £ 17.22, ¥ 2,196.80) + |
release price (tray) | $ 21.26 (€ 19.13, £ 17.22, ¥ 2,196.80) + |
smp max ways | 1 + |
supported memory type | SDR-166 + and DDR-400 + |
tdp | 1.35 W (1,350 mW, 0.00181 hp, 0.00135 kW) + |
tdp (typical) | 0.4 W (400 mW, 5.364e-4 hp, 4.0e-4 kW) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |