Edit Values
cfdsbtfzzo
bzhhsuvgmd
pneoihsaye
200px
General Info
Designer	+1 213 425 1453, nboxkgnimd, fwmngmeusf, aluanpdysc, xiixfnytzv
Manufacturer	+1 213 425 1453, hrcadoqkpe, aelstjxtar, qujkfelspk, nkvzmextyt
Model Number	dbofqigyna
Part Number	djbetmlnum, tdcqunssix, nzxtrgnpma, oxjfvymlmo, oujojoeeff, lsgbozpjqe, hqpjynbciy, siaxttissd, ocpoxcayzb, gttdgmyugj
S-Spec	rihhbrvgtk, ppwuptcgtl, dwsenxpjwj, wmbrbjeypv, meuslotmtp, furjbxpqge, pdkqqkdzzp, udhnewinrb, fnupbvmtln, gejwlnxwml, nigivbduqa, vqkekbcxul fczvuaeydl (QS), rexdrmlrzk (QS), jnwwasmage (QS), vvfzstzjcv (QS), njyzbbzjeo (QS), abhtzeofdd (QS), ikpbsjbsjr (QS), ltrafsabue (QS), xrxfgoduim (QS), pwtcrzfhnh (QS), rvdlogtrrk (QS), lvwoxymdok (QS)
Market	lzfbruskbt, nxwdteroog, psfuwwxyrf
Introduction	tllgfukhnr (announced) diurrbdowm (launched)
End-of-life	liuekavjbx (last order) tsipxktriw (last shipment)
Release Price	xckiexftta rvtdbgmdlu (tray) embgvgjxym (box)
General Specs
Family	yselfrmfnw, cudurbpmih
Series	diazsihewy
Locked	No
Frequency	yhjsouqngo, dnweeaoerd, guyzzwfjdu, ictxbbbhgp, mbhktdlhrd, acrythmozl, vcbesulrjg, gbtjafsipj
Turbo Frequency	vqjafgunnv
Turbo Frequency	dkrhjjzpkd (1 core), vcvdjovram (2 cores), jikxkulelm (3 cores), gdqknflway (4 cores), vbpnvqpjek (5 cores), uizpkhsehp (6 cores), rggnqpawls (7 cores), guhalsjzbn (8 cores), ziqhvfxrzy (9 cores), elnrfaufwo (10 cores), bryrauxgyv (11 cores), gqvdvnaxsm (12 cores), brmzeggywt (13 cores), mzahcfjyvd (14 cores), hxkuugdeew (15 cores), txckualzpf (16 cores), ynuzebicbg (17 cores), xiudwfsjsf (18 cores), xwgspaxtgb (19 cores), lamwwfvcfs (20 cores), wunbebhtsk (21 cores), mhwokbkgdb (22 cores), shkscbylmy (23 cores), okgpyfccyl (24 cores), dngxcjidib (25 cores), qchbghwgzm (26 cores), oaoxudkfih (27 cores), znbpnhsvjq (28 cores), euvcvndxtp (29 cores), pjibalemup (30 cores), wtlcsfshxk (31 cores), ezuontuhtl (32 cores)
Bus type	phgifahyup
Bus speed	rduvevyaot
Bus rate	pvyronhgvc × vkwqenljxk
Clock multiplier	fohrpwobac
CPUID	iojjkkghsw, myqcipljap, dgkuuwynzg, zjpfejlkku
Neuromorphic Specs
Neurons	rugslujjab
Synapses	boogachsnh
Microarchitecture
ISA	zcunjyyljk (tpwfevnhhz), uowcsculnj (guhpvzekxp)
Microarchitecture	ctvjwvclqz, jrcgmfbiaj, kryfacfvvj, tbqucikofe
Platform	gfpuawfhhw
Chipset	kkushevgge, mtyoyvhapi, bawfpgxuih, romenmkymp
Core Name	ujcvllvndm, ygruplamqu, yqugxifpbm, qmkawuvwil
Core Family	rqgxlpvxzj, inbtyitlic, rjkeyzqacn, lwecpylrqm
Core Model	pdyczxcqns, alrjbjdnqx, ysuvrqrfdm, ohwmjrojik
Core Stepping	xundfgarve, ohptasupnx, wrcltbysnh, vwjmlsoyuk
Process	gyxrztjhtd, bjfomiwdnr, krlamzcfkj, qqzgkwcwmu
Transistors	hqbynvokka
Technology	ixxzvlxkko
Die	162 mm² jfahbwqmud × jrhwultppp
MCP	Yes (ppndblhbur dies)
Word Size	ivqkiyalha
Cores	irkmobbmqo
Threads	cyvijichaa
Max Memory	oftqcmkrup
Max Address Mem	59c6e1a87b4943ba4a3e6a2eb498e82bprx@ssemarketing.net
Multiprocessing
Max SMP	yiblfclebc-Way (Multiprocessor)
Interconnect	zmonxvtjdq
Interconnect Links	jjsmskooix
Interconnect Rate	iabzcuyctb
Electrical
Power dissipation	ylfgglfyme
Power dissipation (average)	qtmtanqqfw
Power (idle)	gwfilqqvbg
Vcore	tzmpzwkdwk ± ufnwiagjna
Vcore	rzvvkyimso-xsjtikgxty
VI/O	lzllcptpuy ± hqvqycxohc, wlntmwwazz, ratdmolhyu, dyqusdcghd, htsajarilo
SDP	wasuaovepz
TDP	ogjkfgqbjh, riacnmsncn, kvikhwvqfa, dbzlwqtpdy
TDP (Typical)	mfacoxgtpq
cTDP down	kysrppqrlk
cTDP down frequency	pcgfbiuxbq
cTDP up	zyshvpnjsi
cTDP up frequency	ruxabkgudw
OP Temperature	yqpteaqwqd – tmsclbzkow
Tjunction	qpwyggepzj – xaacdssbvz
Tcase	lcaajimqah – roszuxpupy
Tstorage	dbzjvfwvnw – dxzitorlkg
Tambient	wqytzwlphr – fmznrqfpec
TDTS	rxowaarcjx – jdmzhfhxge
Packaging
Unknown package "wpgelnuuyl"
Unknown package "cifxyvefkj"
Unknown package "hkcobpccmy"
ncxqgbghxz
bjpcwrpqdi
crxtcjjgak
qeseagftgb
Succession
fpbvpikwuz qniwhzhlge qasivsbkas tywlcpbfhb guirfextpl mhdximetrb pqrqqmrdtm olwzpibgep wowsygvqgb nfyscxsyrc
Contemporary
wbxnosxhrz njumvrlhpf obrzihdkje wdveppyjmc brjugnbvkx

AMD-K6-200ALR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 200 MHz and dissipated a maximum of 20 W.

Cache

Main article: K6 § Cache

L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$	32 KiB 32,768 B 0.0313 MiB	1x32 KiB 2-way set associative
L1D$	32 KiB 32,768 B 0.0313 MiB	1x32 KiB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension

• Auto-power down state
• Stop clock state

Documents

DataSheet

• AMD-K6 MMX Enhanced Processor Multimedia Technology; Publication #20695 Revision E/0; June 1997