Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
ThunderX3 - Marvell
< marvell
Revision as of 21:39, 17 November 2019 by 73.158.167.108 (talk)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
| ThunderX3 | |
| ThunderX3 | |
| Developer | Marvell |
| Manufacturer | TSMC |
| Type | Microprocessors |
| Introduction | 2020 (announced) |
| ISA | ARMv8.2 |
| µarch | Triton |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 7nm FFN TSMC "nmFFNTSMC" is not declared as a valid unit of measurement for this property.
|
| Technology | CMOS |
| Succession | |
| ← | |
| ThunderX2 | |
ThunderX3 is a family of 64-bit multi-core ARM server microprocessors planned by Marvell, succeeding the ThunderX2 line originally released by Cavium, now acquired by Marvell.
Overview
 |
This section is empty; you can help add the missing info by editing this page. |
Hidden category:
Facts about "ThunderX3 - Marvell"
| designer | Marvell + |
| first announced | 2020 + |
| full page name | marvell/thunderx3 + |
| instance of | microprocessor family + |
| instruction set architecture | ARMv8.2 + |
| main designer | Marvell + |
| manufacturer | TSMC + |
| microarchitecture | Triton + |
| name | ThunderX3 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |