| MIPS32
|
| Designer: |
MIPS Technologies, Inc.
|
| Bits: |
32-bits
|
| Introduced: |
1999
|
| Version: |
Revision 5.3
|
| Design: |
RISC
|
| Type: |
Register-Register
|
| Encoding: |
Fixed-length
|
| Branching: |
Condition Register
|
| Endianness: |
Bi-endian
|
| Extensions: |
SPECIAL2, COP2, LWC2, SWC2, LDC2, SDC2
|
Application-specific
extension: |
MIPS16e, MCU, SmartMIPS
|
Multimedia
extension: |
MIPS-3D
|
| Registers
|
| General purpose: |
32
|
| Floating point: |
32
|
| Special purpose: |
PRId
|
|
The MIPS32 instruction set is an instruction set standard published in 1999 that was promulgated by MIPS Technologies after its demerger from Silicon Graphics in 1998. The MIPS32 instruction set was developed along side the MIPS64 Instruction Set which includes 64-bit instructions. The MIP32 standard included coprocessor 0 control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most CPUs. Due to its relative simplicity, the MIP32 instruction set is also the most common instruction set thought in computer architecture university courses.
The latest MIPS32 revision is revision 5, which added a set of new memory-efficient operations for large memory footprint applications.
History
The MIPS32 instruction set architecture was first published in 1999 by MIPS Technologies by it has demerged from Silicon Graphics in 1998. MIPS32 is largely a superset of the MIPS II ISA.
Release 2
Release 2 was first introduced in revision 1 of the MIPS32 ISA in 2002. Release 2 added 20 new instructions: DI, EHB, EI, EXT, INS, JALR.HB, JR.HB, MFHC1, MFHC2, MTHC1, MTHC2, RDHWR, RDPGPR, ROTR, ROTRV, SEB, SEH, SYNCI, WRPGPR, and WSBH. Release 2 also added support for 64-bit FPUs.
Release 3
Release 3 was first introduced in revision 3 of the MIPS32 ISA in 2010. The release added the JALX instruction.
Release 4
Release 4 was skipped because MIPS Technologies was being auctioned off. Officially the reason was given as "Release 4 because the number four is considered by many to be inauspicious or unlucky".[1]
Release 5
Release 5 was announced in late 2012. The release added a new set of instructions called Enhanced Virtual Addressing (EVA) to allow more efficient use of memory of larger footprint kernels. The following EVA Load/Store instructions were added: LBE, LBUE, LHE, LHUE, LWE, SBE, SHE, SWE, CACHEE, PREFE, LLE, SCE, LWLE, LWRE, SWLE, SWRE.
Instructions list
Below is a list of the MIPS32 Instruction Set
Arithmetic instructions
| Mnemonic |
Description
|
| ADD |
Add Word
|
| ADDI |
Add Immediate Word
|
| ADDIU |
Add Immediate Unsigned Word
|
| ADDU |
Add Unsigned Word
|
| CLO |
Count Leading Ones in Word
|
| CLZ |
Count Leading Zeros in Word
|
| DIV |
Divide Word
|
| DIVU |
Divide Unsigned Word
|
| MADD |
Multiply and Add Word to Hi, Lo
|
| MADDU |
Multiply and Add Unsigned Word to Hi, Lo
|
| MSUB |
Multiply and Subtract Word to Hi, Lo
|
| MSUBU |
Multiply and Subtract Unsigned Word to Hi, Lo
|
| MUL |
Multiply Word to GPR
|
| MULT |
Multiply Word
|
| MULTU |
Multiply Unsigned Word
|
| SEB |
Sign-Extend Byte
|
| SEH |
Sign-Extend Halftword
|
| SLT |
Set on Less Than
|
| SLTI |
Set on Less Than Immediate
|
| SLTIU |
Set on Less Than Immediate Unsigned
|
| SLTU |
Set on Less Than Unsigned
|
| SUB |
Subtract Word
|
| SUBU |
Subtract Unsigned Word
|
Branch instructions
Note that all the likely branches have been obsoleted; they will be removed in future revisions of the MIPS32 architecture. Software is strongly discouraged from using these instructions.
| Mnemonic |
Description
|
| B |
Unconditional Branch
|
| BAL |
Branch and Link
|
| BEQ |
Branch on Equal
|
| BGEZ |
Branch on Greater Than or Equal to Zero
|
| BGEZAL |
Branch on Greater Than or Equal to Zero and Link
|
| BGTZ |
Branch on Greater Than Zero
|
| BLEZ |
Branch on Less Than or Equal to Zero
|
| BLTZ |
Branch on Less Than Zero
|
| BLTZAL |
Branch on Less Than Zero and Link
|
| BNE |
Branch on Not Equal
|
BEQL |
Branch on Equal Likely
|
BGEZALL |
Branch on Greater Than or Equal to Zero and Link Likely
|
BGEZL |
Branch on Greater Than or Equal to Zero Likely
|
BGTZL |
Branch on Greater Than Zero Likely
|
BLEZL |
Branch on Less Than or Equal to Zero Likely
|
BLTZALL |
Branch on Less Than Zero and Link Likely
|
BLTZL |
Branch on Less Than Zero Likely
|
BNEL |
Branch on Not Equal Likely
|
Jump instructions
| Mnemonic |
Description
|
| J |
Jump
|
| JAL |
Jump and Link
|
| JALR |
Jump and Link Register
|
| JALR.HB |
Jump and Link Register with Hazard Barrier
|
| JALX |
Jump and Link Exchange
|
| JR |
Jump Register
|
| JR.HB |
Jump Register with Hazard Barrier
|
Control instructions
| Mnemonic |
Description
|
| EHB |
Execution Hazard Barrier
|
| NOP |
No Operation
|
| PAUSE |
Wait for LLBit to Clear
|
| SSNOP |
Superscalar No Operation
|
Memory control instructions
| Mnemonic |
Description
|
| LB |
Load Byte
|
| LBE |
Load Byte EVA
|
| LBU |
Load Byte Unsigned
|
| LBUE |
Load Byte Unsigned EVA
|
| LH |
Load Halfword
|
| LHE |
Load Halfword EVA
|
| LHU |
Load Halfword Unsigned
|
| LHUE |
Load Halfword Unsigned EVA
|
| LL |
Load Linked Word
|
| LLE |
Load Linked Word-EVA
|
| LW |
Load Word
|
| LWE |
Load Word EVA
|
| LWL |
Load Word Left
|
| LWLE |
Load Word Left EVA
|
| LWR |
Load Word Right
|
| LWRE |
Load Word Right EVA
|
| PREF |
Prefetch
|
| PREFE |
Prefetch-EVA
|
| SB |
Store Byte
|
| SBE |
Store Byte EVA
|
| SC |
Store Conditional Word
|
| SCE |
Store Conditional Word EVA
|
| SH |
Store Halfword
|
| SHE |
Store Halfword EVA
|
| SW |
Store Word
|
| SWE |
Store Word EVA
|
| SWL |
Store Word Left
|
| SWLE |
Store Word Left EVA
|
| SWR |
Store Word Right
|
| SWRE |
Store Word Right EVA
|
| SYNC |
Synchronize Shared Memory
|
| SYNCI |
Synchronize Caches to Make Instruction Writes Effective
|
Logical instruction
| Mnemonic |
Description
|
| AND |
And
|
| ANDI |
And Immediate
|
| LUI |
Load Upper Immediate
|
| NOR |
Not Or
|
| OR |
Or
|
| ORI |
Or Immediate
|
| XOR |
Exclusive Or
|
| XORI |
Exclusive Or Immediate
|
| Mnemonic |
Description
|
| EXT |
Extract Bit Field
|
| INS |
Insert Bit Field
|
| WSBH |
Word Swap Bytes Within Halfwords
|
Move instructions
| Mnemonic |
Description
|
| MFHI |
Move From HI Register
|
| MFLO |
Move From LO Register
|
| MOVF |
Move Conditional on Floating Point False
|
| MOVN |
Move Conditional on Not Zero
|
| MOVT |
Move Conditional on Floating Point True
|
| MOVZ |
Move Conditional on Zero
|
| MTHI |
Move To HI Register
|
| MTLO |
Move To LO Register
|
| RDHWR |
Read Hardware Register
|
Shift instructions
| Mnemonic |
Description
|
| ROTR |
Rotate Word Right
|
| ROTRV |
Rotate Word Right Variable
|
| SLL |
Shift Word Left Logical
|
| SLLV |
Shift Word Left Logical Variable
|
| SRA |
Shift Word Right Arithmetic
|
| SRAV |
Shift Word Right Arithmetic Variable
|
| SRL |
Shift Word Right Logical
|
| SRLV |
Shift Word Right Logical Variable
|
Trap instructions
| Mnemonic |
Description
|
| BREAK |
Breakpoint
|
| SYSCALL |
System Call
|
| TEQ |
Trap if Equal
|
| TEQI |
Trap if Equal Immediate
|
| TGE |
Trap if Greater or Equal
|
| TGEI |
Trap if Greater of Equal Immediate
|
| TGEIU |
Trap if Greater or Equal Immediate Unsigned
|
| TGEU |
Trap if Greater or Equal Unsigned
|
| TLT |
Trap if Less Than
|
| TLTI |
Trap if Less Than Immediate
|
| TLTIU |
Trap if Less Than Immediate Unsigned
|
| TLTU |
Trap if Less Than Unsigned
|
| TNE |
Trap if Not Equal
|
| TNEI |
Trap if Not Equal Immediate
|
FPU instructions
Arithmetic instructions
Branch instructions
| Mnemonic |
Description
|
| BC1F |
Branch on FP False
|
| BC1T |
Branch on FP True
|
BC1FL |
Branch on FP False Likely
|
BC1TL |
Branch on FP True Likely
|
Compare instructions
| Mnemonic |
Description
|
| C.cond.fmt |
Floating Point Compare
|
Convert instructions
| Mnemonic |
Description
|
| ALNV.PS |
Floating Point Align Variable
|
| CEIL.L.fmt |
Floating Point Ceiling Convert to Long Fixed Point
|
| CEIL.W.fmt |
Floating Point Ceiling Convert to Word Fixed Point
|
| CVT.D.fmt |
Floating Point Convert to Double Floating Point
|
| CVT.L.fmt |
Floating Point Convert to Long Fixed Point
|
| CVT.PS.S |
Floating Point Convert Pair to Paired Single
|
| CVT.S.PL |
Floating Point Convert Pair Lower to Single Floating Point
|
| CVT.S.PU |
Floating Point Convert Pair Upper to Single Floating Point
|
| CVT.S.fmt |
Floating Point Convert to Single Floating Point
|
| CVT.W.fmt |
Floating Point Convert to Word Fixed Point
|
| FLOOR.L.fmt |
Floating Point Floor Convert to Long Fixed Point
|
| FLOOR.W.fmt |
Floating Point Floor Convert to Word Fixed Point
|
| PLL.PS |
Pair Lower Lower
|
| PLU.PS |
Pair Lower Upper
|
| PUL.PS |
Pair Upper Lower
|
| PUU.PS |
Pair Upper Upper
|
| ROUND.L.fmt |
Floating Point Round to Long Fixed Point
|
| ROUND.W.fmt |
Floating Point Round to Word Fixed Point
|
| TRUNC.L.fmt |
Floating Point Truncate to Long Fixed Point
|
| TRUNC.W.fmt |
Floating Point Truncate to Word Fixed Point
|
Memory control instructions
| Mnemonic |
Description
|
| LDC1 |
Load Doubleword to Floating Point
|
| LDXC1 |
Load Doubleword Indexed to Floating Point
|
| LUXC1 |
Load Doubleword Indexed Unaligned to Floating Point
|
| LWC1 |
Load Word to Floating Point
|
| LWXC1 |
Load Word Indexed to Floating Point
|
| PREFX |
Prefetch Indexed
|
| SDC1 |
Store Doubleword from Floating Point
|
| SDXC1 |
Store Doubleword Indexed from Floating Point
|
| SUXC1 |
Store Doubleword Indexed Unaligned from Floating Point
|
| SWC1 |
Store Word from Floating Point
|
| SWXC1 |
Store Word Indexed from Floating Point
|
Move instructions
| Mnemonic |
Description
|
| CFC1 |
Move Control Word from Floating Point
|
| CTC1 |
Move Control Word to Floating Point
|
| MFC1 |
Move Word from Floating Point
|
| MFHC1 |
Move Word from High Half of Floating Point Register
|
| MOV.fmt |
Floating Point Move
|
| MOVF.fmt |
Floating Point Move Conditional on Floating Point False
|
| MOVN.fmt |
Floating Point Move Conditional on Not Zero
|
| MOVT.fmt |
Floating Point Move Conditional on Floating Point True
|
| MOVZ.fmt |
Floating Point Move Conditional on Zero
|
| MTC1 |
Move Word to Floating Point
|
| MTHC1 |
Move Word to High Half of Floating Point Register
|
Coprocessor instructions
Branch instructions
| Mnemonic |
Description
|
| BC2F |
Branch on COP2 False
|
| BC2T |
Branch on COP2 True
|
BC2FL |
Branch on COP2 False Likely
|
BC2TL |
Branch on COP2 True Likely
|
Execute instructions
| Mnemonic |
Description
|
| COP2 |
Coprocessor Operation to Coprocessor 2
|
Memory control instructions
| Mnemonic |
Description
|
| DC2 |
Load Doubleword to Coprocessor 2
|
| LWC2 |
Load Word to Coprocessor 2
|
| SDC2 |
Store Doubleword from Coprocessor 2
|
| SWC2 |
Store Word from Coprocessor 2
|
Move instructions
| Mnemonic |
Description
|
| CFC2 |
Move Control Word from Coprocessor 2
|
| CTC2 |
Move Control Word to Coprocessor 2
|
| MFC2 |
Move Word from Coprocessor 2
|
| MFHC2 |
Move Word from High Half of Coprocessor 2 Register
|
| MTC2 |
Move Word to Coprocessor 2
|
| MTHC2 |
Move Word to High Half of Coprocessor 2 Register
|
Privileged instructions
EJTAG instructions
| Mnemonic |
Description
|
| DERET |
Debug Exception Return
|
| SDBBP |
Software Debug Breakpoint
|
References
