Template:mpu The Xeon E5-4650 v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 4S environments. Operating at 2.2 GHz with a turbo boost frequency of 2.8 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	448 KiB 458,752 B 0.438 MiB	14x32 KiB 8-way set associative (per core, write-back)
L1D$	448 KiB 458,752 B 0.438 MiB	14x32 KiB 8-way set associative (per core, write-back)
L2$	3.5 MiB 3,584 KiB 3,670,016 B 0.00342 GiB	14x256 KiB 8-way set associative (per core, write-back)
L3$	35 MiB 35,840 KiB 36,700,160 B 0.0342 GiB	14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR4-2133
Controllers	1
Channels	4
ECC Support	Yes
Max bandwidth	63.58 GiB/s
Bandwidth (single)	15.89 GiB/s
Bandwidth (dual)	31.79 GiB/s
Max memory	1,536 GiB
Physical Address Extensions	46 bit

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 40 Configs x4, x16

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions F16C 16-bit Floating Point Conversion NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions