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Xeon E5-1603 v4 - Intel
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Template:mpu The Xeon E5-1603 v4 is a 64-bit quad-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 1S workstations. Operating at 2.8 GHz with no turbo boost support, this MPU has a TDP of 140 W and is manufactured on a 14 nm process (based on Broadwell). This model has no hyper-threading support.

This specific model appears to be OEM only.

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core, write-back)
L3$ 10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
4x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-1603 v4 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel vpro technologytrue +
has second level address translation supporttrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description20-way set associative +
l3$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
max pcie lanes40 +