Template:mpu The Xeon E5-4610 v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no turbo boost, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	320 KiB 327,680 B 0.313 MiB	10x32 KiB 8-way set associative (per core, write-back)
L1D$	320 KiB 327,680 B 0.313 MiB	10x32 KiB 8-way set associative (per core, write-back)
L2$	2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB	10x256 KiB 8-way set associative (per core, write-back)
L3$	25 MiB 25,600 KiB 26,214,400 B 0.0244 GiB	10x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR4-2133
Controllers	1
Channels	4
ECC Support	Yes
Max bandwidth	63.58 GiB/s
Bandwidth (single)	15.89 GiB/s
Bandwidth (dual)	31.79 GiB/s
Max memory	1,536 GiB
Physical Address Extensions	46 bit

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions F16C 16-bit Floating Point Conversion NX No-eXecute HT Hyper-Threading EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions