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K6-2/300AFR - AMD
Template:mpu K6-2/300AFR was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB of 100 MHz consumed 17.2 W. Note that K6-2/300AFR-66 is an identical model with a multiplier of 4.5 instead of 3 designed to support a 66 MHz bus instead.
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
Gallery
Documents
DataSheet
- AMD-K6-2 Processor Data Sheet; Publication #21850 Revision J/0, February 2000
Facts about "K6-2/300AFR - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |