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Xeon E5-2695 v4 - Intel
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Revision as of 09:59, 19 October 2017 by 95.221.48.238 (talk) (E5v3 and E5v4 CPUs use 2 dual-channel memory controllers instead of 1 quad-channel. For details see Intel Cluster-on-Die technology.)

Template:mpu The Xeon E5-2695 v4 is a 64-bit octadeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.1 GHz with a turbo boost frequency of 3.3 GHz for a single active core, this MPU has a TDP of 120 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 576 KiB
589,824 B
0.563 MiB
18x32 KiB 8-way set associative (per core, write-back)
L1D$ 576 KiB
589,824 B
0.563 MiB
18x32 KiB 8-way set associative (per core, write-back)
L2$ 4.5 MiB
4,608 KiB
4,718,592 B
0.00439 GiB
18x256 KiB 8-way set associative (per core, write-back)
L3$ 45 MiB
46,080 KiB
47,185,920 B
0.0439 GiB
18x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 2
Channels 4 (2 per controller)
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description8-way set associative +
l2$ size4.5 MiB (4,608 KiB, 4,718,592 B, 0.00439 GiB) +
l3$ description20-way set associative +
l3$ size45 MiB (46,080 KiB, 47,185,920 B, 0.0439 GiB) +