Template:mpu R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.

Cache

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB     L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB     L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1600 Supports ECC No Controllers 1 Channels 1 Width 32 bit Max Bandwidth 5.96 GiB/s 6,103.04 MiB/s 6.4 GB/s 6,399.501 MB/s 0.00582 TiB/s 0.0064 TB/s Bandwidth Single 5.96 GiB/s