Semiconductor & Computer Engineering
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R-Car M3 - Renesas
Template:mpu R-Car M3 is a 64-bit hepta-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The M3 incorporates four Cortex-A53 cores, two Cortex-A57, and an additional Cortex-R7 core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.
Facts about "R-Car M3 - Renesas"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car M3 - Renesas#package + |
| core count | 7 + |
| core name | Cortex-A53 +, Cortex-A57 + and Cortex-R7 + |
| core voltage | 0.9 V (9 dV, 90 cV, 900 mV) + |
| designer | Renesas + and ARM Holdings + |
| family | R-Car + |
| first announced | October 19, 2016 + |
| first launched | October 2016 + |
| full page name | renesas/r-car/m3 + |
| has ecc memory support | false + |
| instance of | microprocessor + |
| integrated gpu | PowerVR GX6250 + |
| integrated gpu designer | Imagination Technologies + |
| io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| isa | ARMv8 + |
| isa family | ARM + |
| l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
| l1d$ size | 224 KiB (229,376 B, 0.219 MiB) + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| ldate | October 2016 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max cpu count | 1 + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| microarchitecture | Cortex-A53 +, Cortex-A57 + and Cortex-R7 + |
| model number | M3 + |
| name | R-Car M3 + |
| package | FCBGA-1022 + |
| part number | R8A77960Frequency + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |
| series | 3rd Gen + |
| smp max ways | 1 + |
| supported memory type | LPDDR4-3200 + |
| technology | CMOS + |
| thread count | 7 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
