Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB 4-way set associative write-back L3$ 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB     4x1.5 MiB   write-back

Memory controller

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	Integrated Memory Controller
	Max Type LPDDR3-1866, DDR3L-1600, DDR4-2133 Supports ECC No Max Mem 64 GiB Controllers 1 Channels 2 Max Bandwidth 31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 15.89 GiB/s Double 31.79 GiB/s