-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
AMD-SSA/5-75ABR - AMD
Template:mpu AMD-SSA/5-75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This processor was the first of AMD's brand new K5 microarchitecture designed entirely in-house. The chip operated at 75 MHz.
Contents
Cache
- Main article: K5 § Cache
Cache Info [Edit Values] | ||
L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- P75 P-Rating
- Auto-power down state
- Stop clock state
Gallery
See also
Facts about "AMD-SSA/5-75ABR - AMD"
l1d$ description | 4-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
processor p-rating | P75 + |