Template:mpu Ryzen Threadripper 1900X is a 64-bit deca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1900X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1900X operates at a base frequency of 3.6 GHz with a TDP of 125 W and a Boost frequency of 4 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 960 KiB 983,040 B 0.938 MiB L1I$ 640 KiB 655,360 B 0.625 MiB 10x64 KiB 4-way set associative   L1D$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative write-back L2$ 5 MiB 5,120 KiB 5,242,880 B 0.00488 GiB     10x512 KiB 8-way set associative write-back L3$ 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB     4x8 MiB 16-way set associative