Semiconductor & Computer Engineering
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EPYC 7601 - AMD
Template:mpu EPYC 7601 is a dual-socket 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7601 has a base frequency of 2.2 GHz with a turbo frequency of 3.2 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
Facts about "EPYC 7601 - AMD"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7601 - AMD#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has amd amd-v technology | true + |
| has amd amd-vi technology | true + |
| has amd sensemi technology | true + |
| has ecc memory support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
| max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
| max memory channels | 8 + |
| max pcie lanes | 128 + |
| supported memory type | DDR4-2666 + |