Process Name
1st Production
Lithography	Lithography
	Immersion
	Exposure
Wafer	Type
	Size
Transistor	Type
	Voltage
Fin	Pitch
	Width
	Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

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{{{process 1 date}}}		{{{process 2 date}}}		{{{process 3 date}}}
{{{process 1 wafer type}}}		{{{process 2 wafer type}}}		{{{process 3 wafer type}}}
{{{process 1 wafer size}}}		{{{process 2 wafer size}}}		{{{process 3 wafer size}}}
{{{process 1 wafer type}}}		{{{process 2 wafer type}}}		{{{process 3 wafer type}}}
{{{process 1 volt}}}		{{{process 2 volt}}}		{{{process 3 volt}}}
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{{{process 1 fin width}}}	{{{process 1 fin width Δ}}}	{{{process 2 fin width}}}	{{{process 2 fin width Δ}}}	{{{process 3 fin width}}}	{{{process 3 fin width Δ}}}
{{{process 1 fin height}}}	{{{process 1 fin height Δ}}}	{{{process 2 fin height}}}	{{{process 2 fin height Δ}}}	{{{process 3 fin height}}}	{{{process 3 fin height Δ}}}
{{{process 1 gate len}}}	{{{process 1 gate len Δ}}}	{{{process 2 gate len}}}	{{{process 2 gate len Δ}}}	{{{process 3 gate len}}}	{{{process 3 gate len Δ}}}
{{{process 1 cpp}}}	{{{process 1 cpp Δ}}}	{{{process 2 cpp}}}	{{{process 2 cpp Δ}}}	{{{process 3 cpp}}}	{{{process 3 cpp Δ}}}
{{{process 1 mmp}}}	{{{process 1 mmp Δ}}}	{{{process 2 mmp}}}	{{{process 2 mmp Δ}}}	{{{process 3 mmp}}}	{{{process 3 mmp Δ}}}
{{{process 1 sram hp}}}	{{{process 1 sram hp Δ}}}	{{{process 2 sram hp}}}	{{{process 2 sram hp Δ}}}	{{{process 3 sram hp}}}	{{{process 3 sram hp Δ}}}
{{{process 1 sram hd}}}	{{{process 1 sram hd Δ}}}	{{{process 2 sram hd}}}	{{{process 2 sram hd Δ}}}	{{{process 3 sram hd}}}	{{{process 3 sram hd Δ}}}
{{{process 1 sram lv}}}	{{{process 1 sram lv Δ}}}	{{{process 2 sram lv}}}	{{{process 2 sram lv Δ}}}	{{{process 3 sram lv}}}	{{{process 3 sram lv Δ}}}
{{{process 1 dram}}}	{{{process 1 dram Δ}}}	{{{process 2 dram}}}	{{{process 2 dram Δ}}}	{{{process 3 dram}}}	{{{process 3 dram Δ}}}