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CN5745-1000 SP - Cavium
<
cavium
|
octeon plus
Revision as of 21:43, 28 December 2016 by
ChipIt
(
talk
|
contribs
)
(Created page with "{{cavium title|CN5745-1000 SP}} {{mpu | name = Cavium CN5745-1000 SP | no image = | image = Octeon CN57xx.svg | image size =...")
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Template:mpu
Facts about "
CN5745-1000 SP - Cavium
"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a
container
construct and is provided by
Semantic MediaWiki
.
CN5745-1000 SP - Cavium#package
+
and
CN5745-1000 SP - Cavium#io
+
base frequency
1,000 MHz (1 GHz, 1,000,000 kHz)
+
core count
10
+
designer
Cavium
+
family
OCTEON Plus
+
first announced
June 26, 2007
+
first launched
August 2007
+
full page name
cavium/octeon plus/cn5745-1000bg1217-sp
+
has ecc memory support
true
+
has hardware accelerators for data compression
true
+
has hardware accelerators for data decompression
true
+
has hardware accelerators for network quality of service processing
true
+
has hardware accelerators for tcp packet processing
true
+
has hardware raid 5 support
true
+
has hardware raid 6 support
true
+
instance of
microprocessor
+
isa
MIPS64
+
isa family
MIPS
+
l1$ size
480 KiB (491,520 B, 0.469 MiB)
+
l1d$ size
160 KiB (163,840 B, 0.156 MiB)
+
l1i$ size
320 KiB (327,680 B, 0.313 MiB)
+
l2$ size
2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB)
+
ldate
August 2007
+
main image
+
manufacturer
TSMC
+
market segment
Storage
+
max cpu count
1
+
max memory bandwidth
11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s)
+
max memory channels
2
+
max pcie lanes
8
+
microarchitecture
cnMIPS
+
model number
CN5745-1000 SP
+
name
Cavium CN5745-1000 SP
+
package
FCBGA-1217
+
part number
CN5745-1000BG1217-SP
+
process
90 nm (0.09 μm, 9.0e-5 mm)
+
series
CN57xx
+
smp max ways
1
+
supported memory type
DDR2-800
+
technology
CMOS
+
thread count
10
+
word size
64 bit (8 octets, 16 nibbles)
+