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From WikiChip
					
    CN5840-1000 NSP  - Cavium    
                
                    < cavium | octeon plus
                
	
														
Cache
- Main article: cnMIPS § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||
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Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5840-1000bg1521-nsp&oldid=31919"
Facts about "CN5840-1000 NSP  - Cavium"
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + | 
| l1d$ description | 64-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 64-way set associative + | 
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l2$ description | 8-way set associative + | 
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |